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118 条记录 (耗时 0.043 秒)

    On-chip RF shields with backside redistribution lines
    56.
    发明授权
    On-chip RF shields with backside redistribution lines 有权
    具有背面再分配线的片上RF屏蔽

    公开(公告)号：US07936052B2

    公开(公告)日：2011-05-03

    申请号：US12242487

    申请日：2008-09-30

    申请人： Hans-Joachim Barth ,  Jens Pohl ,  Gottfried Beer ,  Heinrich Koerner

    发明人： Hans-Joachim Barth ,  Jens Pohl ,  Gottfried Beer ,  Heinrich Koerner

    IPC分类号： H01L29/72

    CPC分类号： H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/552 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05569 ,  H01L2924/0002 ,  H01L2224/05552

    摘要： Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

    摘要翻译： 公开了一种片上系统的结构以及片上系统的形成方法。 在一个实施例中，一种制造片上系统的方法包括从衬底的背面形成穿透衬底开口，穿过衬底开口设置在第一和第二区域之间，第一区域包括用于RF电路的装置，第二区域包括第二 区域包括用于其他电路的装置。 该方法还包括在光致抗蚀剂层上形成用于再分配线的图案，设置在背面下方的光致抗蚀剂层，以及用导电材料填充贯通基板开口和再分配线图案。

    Corresponding capacitor arrangement and method for making the same
    57.
    发明授权
    Corresponding capacitor arrangement and method for making the same 有权
    相应的电容器布置及其制造方法

    公开(公告)号：US07915132B2

    公开(公告)日：2011-03-29

    申请号：US12562460

    申请日：2009-09-18

    申请人： Hans-Joachim Barth ,  Helmut Tews

    发明人： Hans-Joachim Barth ,  Helmut Tews

    IPC分类号： H01L21/20

    CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.

    摘要翻译： 本发明涉及一种用于制造电容器装置的方法和相应的电容器装置，其中第一绝缘层形成在载体衬底的表面，并且在所述绝缘体中产生具有多个间隔第一互连的第一电容器电极 层。 使用掩模层，为了揭露多个第一互连的目的，除去第一绝缘层的部分区域，并且在未覆盖的第一互连件的表面上形成电容器电介质之后，形成第二电容器电极 位于涂覆有电容器电介质的第一互连之间的间隔第二互连的多重性。 这种另外简化的制造方法能够实现具有每单位面积的高电容和机械稳定性的电容器的自对准和成本有效的生产。

    Through substrate via semiconductor components
    58.
    发明授权
    Through substrate via semiconductor components 有权
    通过半导体元件的基板

    公开(公告)号：US07786584B2

    公开(公告)日：2010-08-31

    申请号：US11944846

    申请日：2007-11-26

    申请人： Hans-Joachim Barth ,  Jens Pohl

    发明人： Hans-Joachim Barth ,  Jens Pohl

    IPC分类号： H01L23/48 ,  H01L21/44

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2224/05552

    摘要： A structure and method of forming landing pads for through substrate vias in forming stacked semiconductor components are described. In various embodiments, the current invention describes landing pad structures that includes multiple levels of conductive plates connected by vias such that the electrical connection between a through substrate etch and landing pad is independent of the location of the bottom of the through substrate trench.

    摘要翻译： 描述了在形成堆叠的半导体部件中形成通过衬底通孔的着陆焊盘的结构和方法。 在各种实施例中，本发明描述着陆焊盘结构，其包括通过通孔连接的多层导电板，使得贯穿衬底蚀刻和着陆焊盘之间的电连接独立于贯穿衬底沟槽的底部的位置。

    Electrical fuse and associated methods
    60.
    发明授权
    Electrical fuse and associated methods 有权
    电熔丝及相关方法

    公开(公告)号：US07732898B2

    公开(公告)日：2010-06-08

    申请号：US11670770

    申请日：2007-02-02

    申请人： Hans-Joachim Barth

    发明人： Hans-Joachim Barth

    IPC分类号： H01L23/62

    CPC分类号： H01L23/5256 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fuse link of undoped material is connected between first and second doped material contact regions and a layer of conductive material is located above the first and second contact regions and the fuse link. According to other embodiments, a fuse link is connected between first and second contact regions. A layer of conductive material is above the first and second contact regions and the fuse link, and a heat sink is in proximity to the fuse link. In a method, a programming pulse is applied to a fuse link of undoped material connected between first and second doped material contact regions to generate electromigration drift of a conductive material above the first and second contact regions and the fuse link.

    摘要翻译： 未掺杂材料的熔丝连接在第一和第二掺杂材料接触区域之间，并且导电材料层位于第一和第二接触区域和熔丝链的上方。 根据其他实施例，熔丝链路连接在第一和第二接触区域之间。 导电材料层位于第一和第二接触区域和熔断体之上，散热器靠近熔断体。 在一种方法中，将编程脉冲施加到连接在第一和第二掺杂材料接触区域之间的未掺杂材料的熔丝链，以在第一和第二接触区域和熔丝链上方产生导电材料的电迁移漂移。