公开(公告)号：US20050200003A1

公开(公告)日：2005-09-15

申请号：US11033993

申请日：2005-01-13

Applicant: Ki-myung Yoon ,  Heung-kyu Kwon ,  Hee-seok Lee

Inventor： Ki-myung Yoon ,  Heung-kyu Kwon ,  Hee-seok Lee

IPC: H01L25/07 ,  G11C11/34 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/44 ,  H01L21/50 ,  H01L21/52 ,  H01L21/60 ,  H01L23/00 ,  H01L23/12 ,  H01L23/34 ,  H01L23/48 ,  H01L23/488 ,  H01L23/50 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H05K3/30 ,  H05K5/00 ,  H05K5/04 ,  H05K5/06

CPC classification number: G11C16/10 ,  B82Y10/00 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2216/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48265 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19102 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A multi-chip package may be provided which may include a substrate, on which multiple substrate bonding pads may be formed and under which multiple terminals may be formed, first and second semiconductor chips, which may be deposited on the substrate, and a spacer, which may be formed between the first and second semiconductor chips to have at least power and ground pads. The spacer may be used as passive element, and the first and second semiconductor chips and the power and ground pads of the spacer may be electrically connected. The pads of the semiconductor chip which may be deposited on the spacer may also be electrically connected to substrate bonding pads via the pads which may be formed on the spacer.

Abstract translation: 可以提供多芯片封装，其可以包括可以形成多个基板接合焊盘并且可以在其下形成多个端子的基板，可以沉积在基板上的第一和第二半导体芯片以及间隔件， 其可以形成在第一和第二半导体芯片之间以具有至少电源和接地焊盘。 间隔件可以用作无源元件，并且间隔件的第一和第二半导体芯片以及电源和接地焊盘可以电连接。 可以沉积在间隔物上的半导体芯片的焊盘也可以经由可以形成在间隔物上的焊盘电连接到衬底焊盘。

公开(公告)号：US20140319701A1

公开(公告)日：2014-10-30

申请号：US14132516

申请日：2013-12-18

Applicant: Yong-hoon Kim ,  Hyo-soon Kang ,  Hee-seok Lee ,  Jang-ho Cho

Inventor： Yong-hoon Kim ,  Hyo-soon Kang ,  Hee-seok Lee ,  Jang-ho Cho

IPC: H01L25/18 ,  H01L23/50

CPC classification number: H01L25/18 ,  G11C5/025 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.

Abstract translation: 一种半导体芯片，包括衬底，布置在衬底上的第一数据焊盘和布置在衬底上的第一控制/寻址焊盘，其中第一数据焊盘布置在衬底的边缘区域中，并且第一控制/地址焊盘 布置在基板的中心区域中。

公开(公告)号：US08873245B2

公开(公告)日：2014-10-28

申请号：US13113239

申请日：2011-05-23

Applicant: Yong-hoon Kim ,  Hee-seok Lee

Inventor： Yong-hoon Kim ,  Hee-seok Lee

IPC: H05K1/18 ,  H01L25/10 ,  H01L25/065 ,  H05K3/34 ,  H05K3/28

CPC classification number: H05K1/183 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An embedded chip-on-chip package includes a printed circuit board having a recessed semiconductor chip mounting unit constituted by a recess in the printed circuit board and a circuit pattern at the bottom of the recess, a first semiconductor chip embedded in the recessed semiconductor chip mounting unit and electrically connected to the circuit pattern at the bottom of the recess, and a second semiconductor chip mounted to the recessed semiconductor chip mounting unit and electrically connected to the first semiconductor chip and the printed circuit board independently of each other.

Abstract translation: 嵌入式芯片芯片封装包括印刷电路板，其具有由印刷电路板中的凹部构成的凹陷半导体芯片安装单元和凹部底部的电路图案，嵌入在凹陷半导体芯片中的第一半导体芯片 安装单元，并且电连接到凹部的底部处的电路图案，以及安装到凹陷半导体芯片安装单元并且彼此独立地电连接到第一半导体芯片和印刷电路板的第二半导体芯片。

公开(公告)号：US08502084B2

公开(公告)日：2013-08-06

申请号：US12772385

申请日：2010-05-03

Applicant: Eun seok Song ,  Hee seok Lee ,  Hyun-a Kim ,  So-young Lim

Inventor： Eun seok Song ,  Hee seok Lee ,  Hyun-a Kim ,  So-young Lim

IPC: H05K1/11

CPC classification number: H01L23/50 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48233 ,  H01L2224/48235 ,  H01L2224/48237 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor chip carrier having multiple conductive layers separated from each other by dielectric layers, a chip bonding position at an intermediate portion of a top surface of the semiconductor chip carrier, and a bonding region spaced apart from the chip bonding position. The bonding region includes a first bonding region closest to the chip bonding position, a second bonding region most distant from the chip bonding position, and a third bonding region positioned between the first bonding region and the second bonding region. The first bonding region, the second bonding region and the third bonding region are electrically insulated from each other and the first bonding region is configured to carry a first voltage, the second bonding region is configured to carry a second voltage and the third bonding region is configured to carry a third voltage that is less than the first voltage and less than the second voltage.

Abstract translation: 一种半导体芯片载体，其具有通过电介质层彼此分离的多个导电层，在半导体芯片载体的上表面的中间部分处的芯片接合位置以及与芯片接合位置间隔开的接合区域。 接合区域包括最靠近芯片接合位置的第一接合区域，最靠近芯片接合位置的第二接合区域和位于第一接合区域和第二接合区域之间的第三接合区域。 第一接合区域，第二接合区域和第三接合区域彼此电绝缘，并且第一接合区域被配置为承载第一电压，第二接合区域被配置为承载第二电压，并且第三接合区域是 被配置为承载小于所述第一电压并小于所述第二电压的第三电压。

公开(公告)号：US08445996B2

公开(公告)日：2013-05-21

申请号：US12568224

申请日：2009-09-28

Applicant: Yong-hoon Kim ,  Hee-seok Lee ,  Yun-seok Choi

Inventor： Yong-hoon Kim ,  Hee-seok Lee ,  Yun-seok Choi

IPC: H01L23/60

CPC classification number: H01L23/552 ,  H01L23/60 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor package includes a main substrate, a semiconductor chip having a first side and a second side, the first side of the semiconductor chip disposed on the main substrate and electrically connected to the main substrate, and a conductive network formed on the second side of the semiconductor chip.

Abstract translation: 半导体封装包括主衬底，具有第一侧和第二侧的半导体芯片，设置在主衬底上并与主衬底电连接的半导体芯片的第一侧和形成在主衬底的第二侧上的导电网络 半导体芯片。

公开(公告)号：US08253228B2

公开(公告)日：2012-08-28

申请号：US13045103

申请日：2011-03-10

Applicant: Yong-Hoon Kim ,  Byeong-Yeon Cho ,  Hee-Seok Lee

Inventor： Yong-Hoon Kim ,  Byeong-Yeon Cho ,  Hee-Seok Lee

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0652 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A package on package structure includes a lower package and an upper package. The lower package includes a first semiconductor chip disposed in a chip region of an upper surface of a first substrate. The upper package includes a second semiconductor chip disposed on an upper surface of a second substrate, and a decoupling capacitor disposed in an outer region of a lower surface of the second substrate. The lower surface of the second substrate opposes the upper surface of the second substrate and faces the upper surface of the first substrate. The plane area of the second substrate is larger than the plane area of the first substrate. The outer region of the lower surface of the second substrate extends beyond a periphery of the first substrate.

Abstract translation: 包装结构上的包装包括下包装和上包装。 下封装包括设置在第一基板的上表面的芯片区域中的第一半导体芯片。 上部封装包括设置在第二基板的上表面上的第二半导体芯片和设置在第二基板的下表面的外部区域中的去耦电容器。 第二基板的下表面与第二基板的上表面相对并且面向第一基板的上表面。 第二基板的平面面积大于第一基板的平面面积。 第二基板的下表面的外部区域延伸超出第一基板的周边。

公开(公告)号：US20120139090A1

公开(公告)日：2012-06-07

申请号：US13243704

申请日：2011-09-23

Applicant: Yong-Hoon Kim ,  Hee-Seok Lee ,  Seong-Ho Shin ,  Se-Ho You ,  Yun-Hee Lee

Inventor： Yong-Hoon Kim ,  Hee-Seok Lee ,  Seong-Ho Shin ,  Se-Ho You ,  Yun-Hee Lee

IPC: H01L23/552

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/552 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package.

Abstract translation: 提供堆叠的包装结构。 堆叠封装结构包括：堆叠封装，包括下半导体封装，设置在下半导体封装上并与下半导体封装隔开预定距离的上半导体封装;电连接下半导体封装和 上部半导体封装，同时支撑它们之间的空间，以及绝缘层，其至少设置在所述封装间连接部分的外部并填充所述下部半导体封装和所述上部半导体封装之间的空间，以及围绕所述下部半导体封装的横向和顶部表面的电磁屏蔽层 堆叠包装。

公开(公告)号：US20120080222A1

公开(公告)日：2012-04-05

申请号：US13247526

申请日：2011-09-28

Applicant: Yong-Hoon Kim ,  Hee-Seok Lee ,  Ji-Hyun Lee

Inventor： Yong-Hoon Kim ,  Hee-Seok Lee ,  Ji-Hyun Lee

IPC: H05K1/16

CPC classification number: H05K1/0231 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4644

Abstract: A circuit board including an embedded decoupling capacitor and a semiconductor package thereof are provided. The circuit board may include a core layer including an embedded decoupling capacitor, a first build-up layer at one side of the core layer, and a second build-up layer at the other side of the core layer, wherein the embedded decoupling capacitor includes a first electrode and a second electrode, the first build-up layer includes a first via contacting the first electrode, and the second build-up layer includes a second via contacting the first electrode.

Abstract translation: 提供了包括嵌入式去耦电容器及其半导体封装的电路板。 电路板可以包括芯层，其包括嵌入的去耦电容器，在芯层的一侧的第一累积层和在芯层的另一侧的第二堆叠层，其中嵌入的去耦电容器包括 第一电极和第二电极，所述第一堆积层包括与所述第一电极接触的第一通孔，并且所述第二堆积层包括与所述第一电极接触的第二通路。

公开(公告)号：US08120024B2

公开(公告)日：2012-02-21

申请号：US11758176

申请日：2007-06-05

Applicant: Eun-seok Song ,  Dong-han Kim ,  Hee-seok Lee

Inventor： Eun-seok Song ,  Dong-han Kim ,  Hee-seok Lee

IPC: H01L23/58

CPC classification number: G01R31/2884 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.

Abstract translation: 公开了半导体封装和测试方法。 封装包括具有顶表面和底表面的衬底，安装在衬底的位于中心的半导体芯片安装区域中的半导体芯片以及设置在衬底的顶表面和底表面上的多个测试焊盘，并且包括第一组测试焊盘 配置在衬底的顶表面和底表面上并且具有在衬底的相应顶部和底部表面上方的第一高度，以及设置在衬底的下表面上并具有大于第一衬底的第二高度的第二组测试焊盘 其中第二组测试垫中的每一个包括附接到其上的焊球。

公开(公告)号：US20110317381A1

公开(公告)日：2011-12-29

申请号：US13113239

申请日：2011-05-23

Applicant: Yong-hoon KIM ,  Hee-seok LEE

Inventor： Yong-hoon KIM ,  Hee-seok LEE

IPC: H05K1/18

CPC classification number: H05K1/183 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An embedded chip-on-chip package comprises a printed circuit board having a recessed semiconductor chip mounting unit, a first semiconductor chip embedded in the recessed semiconductor chip mounting unit, and a second semiconductor chip mounted on the first semiconductor chip and the printed circuit board.

Abstract translation: 嵌入式芯片芯片封装包括具有凹入的半导体芯片安装单元的印刷电路板，嵌入在凹陷半导体芯片安装单元中的第一半导体芯片以及安装在第一半导体芯片和印刷电路板上的第二半导体芯片 。