公开(公告)号：US09000579B2

公开(公告)日：2015-04-07

申请号：US11694912

申请日：2007-03-30

申请人： Il Kwon Shim ,  Dario S. Filoteo, Jr. ,  Emmanuel Espiritu ,  Rachel Layda Abinan

发明人： Il Kwon Shim ,  Dario S. Filoteo, Jr. ,  Emmanuel Espiritu ,  Rachel Layda Abinan

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/44 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85186 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.

摘要翻译： 一种集成电路封装系统，包括其中设置有开口的基板，在该开口中形成在底部具有封闭端的导体，将集成电路裸片安装在基板上，并将芯片互连连接到集成电路管芯和封闭 导体末端。

公开(公告)号：US08957530B2

公开(公告)日：2015-02-17

申请号：US13023293

申请日：2011-02-08

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Seung Uk Yoon ,  Jong-Woo Ha

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Seung Uk Yoon ,  Jong-Woo Ha

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L24/19 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/82 ,  H01L2924/00

摘要： An integrated circuit packaging system includes: an integrated circuit device; a conductive post adjacent the integrated circuit device, the conductive post with a contact surface having characteristics of a shaped platform removed; and an encapsulant around the conductive post and the integrated circuit device with the conductive post extending through the encapsulant and each end of the conductive post exposed from the encapsulant.

摘要翻译： 一种集成电路封装系统，包括：集成电路器件; 邻近集成电路器件的导电柱，具有去除成形平台特征的接触表面的导电柱; 以及围绕导电柱和集成电路器件的密封剂，其中导电柱延伸穿过密封剂并且从密封剂暴露出的导电柱的每个端部。

公开(公告)号：US08951834B1

公开(公告)日：2015-02-10

申请号：US13931295

申请日：2013-06-28

申请人： Kyung Moon Kim ,  Il Kwon Shim ,  HeeJo Chi ,  HanGil Shin

发明人： Kyung Moon Kim ,  Il Kwon Shim ,  HeeJo Chi ,  HanGil Shin

IPC分类号： H01L21/00 ,  G01R31/26 ,  H01L21/66 ,  H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56

CPC分类号： H01L21/565 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/00

摘要： Methods of forming solder balls for semiconductor packages using film-assisted molding include providing a substrate, forming a plurality of solder balls on the substrate where each solder ball has an initial profile, and coupling a substantially planar film to the solder balls. As an encapsulation is deposited over the substrate and around the solder balls, the substantially planar film and the encapsulation, along with the molding process, can cause each solder ball to morph from its initial profile to a final profile, where the final profile is generally different from the initial profile.

摘要翻译： 使用膜辅助成型形成用于半导体封装的焊球的方法包括提供衬底，在衬底上形成多个焊球，其中每个焊球具有初始形状，并将基本上平面的膜耦合到焊球。 当封装沉积在衬底上并且在焊球周围时，基本平坦的膜和封装以及模制过程可以使每个焊球从其初始轮廓变形到最终轮廓，其中最终轮廓通常 与初始配置文件不同。

公开(公告)号：US08912648B2

公开(公告)日：2014-12-16

申请号：US13231789

申请日：2011-09-13

申请人： Yaojian Lin ,  Il Kwon Shim ,  Seng Guan Chow

发明人： Yaojian Lin ,  Il Kwon Shim ,  Seng Guan Chow

IPC分类号： H01L23/04 ,  H01L23/16 ,  H01L23/00 ,  H01L21/56 ,  H01L23/552 ,  H01L23/31 ,  H01L21/683

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer.

摘要翻译： 半导体器件具有在指定用于凸块形成的位置中安装到临时衬底的应力释放缓冲器。 应力消除缓冲器可以是多层复合材料，例如第一顺应层，在第一柔性层上形成的硅层，以及形成在硅层上的第二柔性层。 半导体管芯也安装在临时衬底上。 应力消除缓冲器可以比半导体管芯更薄。 密封剂沉积在半导体管芯和应力释放缓冲器之间。 移除临时衬底。 在半导体管芯，密封剂和应力释放缓冲器上形成互连结构。 互连结构电连接到半导体管芯。 可以在应力消除缓冲器和密封剂上形成加强层。 可以在应力消除缓冲器内形成包含有源器件，无源器件，导电层和电介质层的电路层。

公开(公告)号：US08659113B2

公开(公告)日：2014-02-25

申请号：US13446741

申请日：2012-04-13

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L29/00

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.

摘要翻译： 嵌入式半导体管芯封装通过使用粘合剂将框架载体安装到临时载体上而制成。 框架载体包括每个包括围绕腔的引线框架互连结构的管芯安装位置。 半导体管芯设置在每个腔中。 将密封剂沉积在模具上的空腔中。 封装互连结构形成在引线框架互连结构和密封剂上。 封装互连结构和引线框互连结构电连接到管芯。 帧载体被分成单独的嵌入式芯片封装。 半导体管芯可以垂直堆叠或并排放置在腔内。 嵌入式管芯封装可以通过引线框互连结构堆叠并电互连。 半导体器件可以安装到嵌入式裸片封装并且通过引线框互连结构电连接到裸片。

公开(公告)号：US20130320525A1

公开(公告)日：2013-12-05

申请号：US13842582

申请日：2013-03-15

申请人： Yaojian Lin ,  Il Kwon Shim ,  JunMo Koo ,  Jose Alvin Caparas

发明人： Yaojian Lin ,  Il Kwon Shim ,  JunMo Koo ,  Jose Alvin Caparas

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L23/49811 ,  H01L21/76885 ,  H01L23/16 ,  H01L23/49816 ,  H01L24/19 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00

摘要： An integrated circuit packaging system and method of manufacture thereof includes: a substrate having a top insulation layer and a top conductive layer; an inter-react layer on the substrate; an integrated circuit die on the substrate; a package body on the inter-react layer and the integrated circuit die; and a top solder bump on the top conductive layer, the top solder bump in a 3D via formed through the package body, the inter-react layer, and the top insulation layer for exposing the top conductive layer in the 3D via.

摘要翻译： 集成电路封装系统及其制造方法包括：具有顶部绝缘层和顶部导电层的衬底; 基板上的反应间层; 集成电路裸片在基板上; 反应层间和集成电路管芯上的封装体; 以及顶部导电层上的顶部焊料凸块，通过封装主体，反应间层和顶部绝缘层形成的3D通孔中的顶部焊料凸块，用于暴露3D通孔中的顶部导电层。

公开(公告)号：US08587098B2

公开(公告)日：2013-11-19

申请号：US13154308

申请日：2011-06-06

申请人： Seng Guan Chow ,  Ming Ying ,  Il Kwon Shim ,  Roger Emigh

发明人： Seng Guan Chow ,  Ming Ying ,  Il Kwon Shim ,  Roger Emigh

IPC分类号： H01L23/495 ,  H01L21/44

CPC分类号： H01L21/565 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing an integrated circuit package system includes: providing a leadframe; forming a protruding pad on the leadframe; attaching a die to the leadframe; electrically connecting the die to the leadframe; and encapsulating at least portions of the leadframe, the protruding pad, and the die in an encapsulant.

摘要翻译： 一种用于制造集成电路封装系统的方法，包括：提供引线框架; 在引线框上形成突出的焊盘; 将模具附接到引线框架; 将管芯电连接到引线框架; 并且将引线框，突出垫和模具的至少一部分封装在密封剂中。

公开(公告)号：US20130113092A9

公开(公告)日：2013-05-09

申请号：US13333739

申请日：2011-12-21

申请人： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

发明人： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC分类号： H01L23/52 ,  H01L21/56 ,  H01L21/78

CPC分类号： H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

摘要： A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

摘要翻译： 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。

公开(公告)号：US08399968B2

公开(公告)日：2013-03-19

申请号：US11164335

申请日：2005-11-18

申请人： Jeffrey D. Punzalan ,  Henry D. Bathan ,  Il Kwon Shim

发明人： Jeffrey D. Punzalan ,  Henry D. Bathan ,  Il Kwon Shim

IPC分类号： H01L23/495

CPC分类号： H01L23/49503 ,  H01L23/49541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A non-leaded integrated circuit package system is provided providing a die paddle of a lead frame, forming a dual row of terminals including outer terminal pads and inner terminal pads, and selectively fusing an extension between the die paddle and instances of the inner terminal pads.

摘要翻译： 提供了一种非引线集成电路封装系统，其提供引线框架的管芯焊盘，形成包括外部端子焊盘和内部端子焊盘的双排端子，并且选择性地熔合管芯焊盘与内部端子焊盘的实例之间的延伸 。

公开(公告)号：US08354304B2

公开(公告)日：2013-01-15

申请号：US12329430

申请日：2008-12-05

申请人： Seng Guan Chow ,  Il Kwon Shim ,  Heap Hoe Kuan ,  Rui Huang

发明人： Seng Guan Chow ,  Il Kwon Shim ,  Heap Hoe Kuan ,  Rui Huang

IPC分类号： H01L21/00

CPC分类号： H01L23/49811 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a post carrier having a base plate and plurality of conductive posts. A photosensitive encapsulant is deposited over the base plate of the post carrier and around the conductive posts. The photosensitive encapsulant is etched to expose a portion of the base plate of the post carrier. A semiconductor die is mounted to the base plate of the post carrier within the etched portions of the photosensitive encapsulant. A second encapsulant is deposited over the semiconductor die. A first circuit build-up layer is formed over the second encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. The base plate of the post carrier is removed and a second circuit build-up layer is formed over the semiconductor die and the photosensitive encapsulant opposite the first circuit build-up layer. The second circuit build-up layer is electrically connected to the conductive posts.