公开(公告)号：US10340247B2

公开(公告)日：2019-07-02

申请号：US15705894

申请日：2017-09-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L27/06

Abstract: A method for forming a semiconductor device structure and method for forming the same are provided. The method includes hybrid bonding a first wafer and a second wafer to form a hybrid bonding structure, and the hybrid bonding structure comprises a metallic bonding interface and a polymer-to-polymer bonding structure. The method includes forming at least one through-substrate via (TSV) through the second wafer, and the TSV extends from a bottom surface of the second wafer to a top surface of the first wafer.

公开(公告)号：US10276516B2

公开(公告)日：2019-04-30

申请号：US15966382

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/03 ,  H01L25/065 ,  H01L25/10

Abstract: Some embodiments relate to a semiconductor package. The semiconductor package includes a redistribution layer (RDL) including a first metal layer and a second metal layer. The second metal layer is stacked over the first metal layer and is coupled to the first metal layer through a via. A first semiconductor die is disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL, and the RDL enables fan-out connection of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die and over the RDL. The second semiconductor die is bonded to the RDL by a plurality of conductive bump structures.

公开(公告)号：US20190123015A1

公开(公告)日：2019-04-25

申请号：US16218495

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Li-Hui Cheng ,  Po-Hao Tsai ,  Chih-Chien Pan

IPC: H01L23/00 ,  H01L21/67 ,  H01L25/10 ,  H01L21/56 ,  H01L21/78

Abstract: A printing module, printing method and system of forming a printed structure are provided. The printing module includes a first printing dispenser operable to dispense a first material, a second printing dispenser operable to dispense a second material, a first curing unit, a second curing unit and a third curing unit. The first, the second and the third curing units each is operable to irradiate a light capable of curing the first and second materials and are alternately arranged with the first and second printing dispensers along a line. The first and second printing dispensers and the first, second and third curing units are simultaneously movable along the line. During the second curing unit and one of the first curing unit and the third curing unit are operable to irradiate the light, the other of the first curing unit and the third curing unit is off.

公开(公告)号：US20190103387A1

公开(公告)日：2019-04-04

申请号：US15854755

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Ju Tsou ,  Chih-Wei Wu ,  Jing-Cheng Lin ,  Pu Wang ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

Abstract: Provided are a PoP device and a method of manufacturing the same. The PoP device includes a first package structure and a second package structure. The first package structure includes a die, a through integrated fan-out via (TIV), an encapsulant, and a film. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The film is over the TIV and the encapsulant, and aside the die. The second package structure is connected to the first package structure through a connector. The connector penetrates through the film to electrically connected to the TIV.

公开(公告)号：US20190096851A1

公开(公告)日：2019-03-28

申请号：US15716506

申请日：2017-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Hang Liao ,  Chih-Wei Wu ,  Jing-Cheng Lin ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3128 ,  H01L25/065 ,  H01L2221/68345

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge, an underfill layer and a RDL structure. The first die and the second die are placed side by side. The first encapsulant encapsulates sidewalls of the first die and sidewalls of the second die. The bridge electrically connects the first die and the second die through two conductive bumps. The underfill layer fills the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsualnt. The RDL structure is located over the bridge and electrically connected to the first die and the second die though a plurality of TIVs. The bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.

公开(公告)号：US20180197826A1

公开(公告)日：2018-07-12

申请号：US15911765

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/562 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/11464 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Some embodiments of the present disclosure relate to an integrated circuit. The integrated circuit has a first semiconductor die and a second semiconductor die. The first semiconductor die is bonded to the second semiconductor die by one or more bonding structures. A first plurality of support structures are disposed between the first semiconductor die and the second semiconductor die. The first plurality of support structures are spaced apart from the one or more bonding structures. The first plurality of support structures are configured to hold together the first semiconductor die and the second semiconductor die.

公开(公告)号：US09991244B2

公开(公告)日：2018-06-05

申请号：US14752342

申请日：2015-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Jing-Cheng Lin

IPC: H01L21/768 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/89 ,  H01L25/0657 ,  H01L2224/0231 ,  H01L2224/08145 ,  H01L2224/80815 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/0002 ,  H01L2924/1304 ,  H01L2924/00

Abstract: Method for forming a semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a first polymer material and a second conductive material embedded in a second polymer material. The first conductive material is bonded to the second conductive material and the first polymer material is bonded to the second polymer material. The semiconductor device also includes at least one through silicon via (TSV) extending from a bottom surface of the first semiconductor wafer to a metallization structure of the first semiconductor wafer. The semiconductor device structure also includes an interconnect structure formed over the bottom surface of the first semiconductor wafer, and the interconnect structure is electrically connected to the metallization structure via the TSV.

公开(公告)号：US20180006005A1

公开(公告)日：2018-01-04

申请号：US15235118

申请日：2016-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hui Cheng ,  Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L25/00 ,  H01L21/50 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/60

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2021/6009 ,  H01L2021/6024 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/02311 ,  H01L2224/13024

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.

公开(公告)号：US09502380B2

公开(公告)日：2016-11-22

申请号：US14959094

申请日：2015-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Shang-Yun Hou

IPC: H01L21/50 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00 ,  H01L21/683 ,  H01L21/60

CPC classification number: H01L25/0652 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2021/6006 ,  H01L2021/6024 ,  H01L2224/02331 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05541 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32227 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the method is performed by placing an interposer with one or more through-substrate-vias (TSVs) on a first adhesive layer overlying a first carrier substrate. Connection structures are arranged along a first surface of the interposer facing the first adhesive layer. A first molding compound is formed over the first adhesive layer and surrounding the interposer. The first molding compound is arranged to expose the TSVs along a second surface of the interposer. A first redistribution structure is formed over the second surface of the interposer and the first molding compound, and conductive bump structures are formed over the first redistribution structure. A first packaged die is bonded to the conductive bump structures.

Abstract translation: 提供一种半导体封装以及通过中介层形成具有一个或多个管芯的半导体封装的方法。 在一些实施例中，通过将具有一个或多个贯穿衬底通孔（TSV）的插入件放置在覆盖在第一载体衬底上的第一粘合剂层上来执行该方法。 连接结构沿着面向第一粘合剂层的中介层的第一表面布置。 在第一粘合剂层上形成第一模塑料并围绕插入件。 第一模塑料被布置成沿着插入件的第二表面暴露TSV。 第一再分配结构形成在插入件的第二表面和第一模塑料上，并且在第一再分配结构上形成导电凸块结构。 第一封装管芯结合到导电凸块结构。

公开(公告)号：US20160336280A1

公开(公告)日：2016-11-17

申请号：US15219593

申请日：2016-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/27 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82 ,  H01L2224/82005 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00011

Abstract: A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure.