公开(公告)号：US07866800B2

公开(公告)日：2011-01-11

申请号：US12288056

申请日：2008-10-16

Applicant: Tomoyuki Kubo ,  Koji Imai

Inventor： Tomoyuki Kubo ,  Koji Imai

IPC: B41J2/045 ,  B21D53/76

CPC classification number: B41J2/1609 ,  B41J2/14209 ,  B41J2/1623 ,  B41J2/1631 ,  B41J2002/14217 ,  B41J2002/14225 ,  B41J2002/14306 ,  B41J2002/14419 ,  B41J2002/14491 ,  H05K1/092 ,  H05K3/245 ,  H05K3/3452 ,  H05K3/363 ,  H05K2201/09427 ,  H05K2201/099 ,  H05K2203/0465 ,  Y10T29/49401

Abstract: A liquid droplet jetting apparatus includes: a liquid droplet jetting head which jets liquid droplets when an actuator is driven; and a wiring member via which a drive signal is outputted to a surface electrode formed in the actuator. The wiring member includes a substrate, a wire provided on the substrate, and a covering member having an insulating property and covering the wire. The wire has an electrode land which is stacked on the surface electrode to be connected to the surface electrode, and the covering member has a first covering layer in which a first opening to expose the electrode land therein is formed and a second covering layer having a second opening communicating with the first opening and covering the first covering layer. The surface electrode and the electrode land are connected in a state that an electroconductive material is interposed therebetween through the first and second openings.

Abstract translation: 液滴喷射装置包括：液滴喷射头，其在致动器被驱动时喷射液滴; 以及通过其将驱动信号输出到形成在致动器中的表面电极的配线构件。 布线构件包括基板，设置在基板上的线材和具有绝缘性且覆盖线材的覆盖部件。 导线具有层叠在表面电极上以与表面电极连接的电极焊盘，并且覆盖部件具有第一覆盖层，其中形成有第一开口以暴露其中的电极焊盘;以及第二覆盖层，其具有 第二开口与第一开口连通并覆盖第一覆盖层。 表面电极和电极焊盘之间通过第一和第二开口插入导电材料的状态下连接。

公开(公告)号：US20100290203A1

公开(公告)日：2010-11-18

申请号：US12762123

申请日：2010-04-16

Applicant: Osamu Nagasaki

Inventor： Osamu Nagasaki

IPC: H05K7/02

CPC classification number: H05K3/3468 ,  G03G15/80 ,  H01L2924/0002 ,  H05K1/0259 ,  H05K1/111 ,  H05K1/116 ,  H05K3/3447 ,  H05K3/3452 ,  H05K2201/09463 ,  H05K2201/09781 ,  H05K2201/09854 ,  H05K2201/099 ,  H05K2201/10083 ,  H05K2201/10689 ,  H05K2201/1081 ,  H05K2203/044 ,  H05K2203/046 ,  H01L2924/00

Abstract: An electronic apparatus includes, for example, a circuit board with an electronic component and a piezoelectric element, a reference potential pattern that gives a reference potential to at least one of the electronic component and the piezoelectric element, and a solder land connected to the reference potential pattern. On the circuit board, the electronic component is located on a downstream side in a transport direction of the circuit board during mounting of the piezoelectric element and the electronic component on the solder land, and the piezoelectric element is located on an upstream side in the transport direction.

Abstract translation: 电子设备例如包括具有电子部件和压电元件的电路板，向电子部件和压电元件中的至少一个赋予参考电位的基准电位图形以及连接到基准电极的焊接焊盘 潜在的模式。 在电路板上，电子部件在将压电元件和电子部件安装在焊锡焊盘上时位于电路基板的输送方向的下游侧，压电元件位于输送路径的上游侧 方向。

公开(公告)号：US07768131B1

公开(公告)日：2010-08-03

申请号：US12493171

申请日：2009-06-27

Applicant: Jun-Chung Hsu ,  Chen-Lin Li

Inventor： Jun-Chung Hsu ,  Chen-Lin Li

IPC: H01L23/48

CPC classification number: H05K3/341 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/10175 ,  H01L2224/16 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01078 ,  H05K3/3436 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/099 ,  Y02P70/613 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A package structure preventing solder overflow on substrate solder pads includes a plurality of die pins, a plurality of solders and a plurality of substrate solder pads. The die pins are located under a die. The substrate solder pads are formed on an upper surface of a substrate by copper plating or etching. Each of the substrate solder pads has at least one solder pad connection point. The solders connect the die pins with the corresponding solder pad connection points, respectively. Each of the solder pad connection points has a pair of solder pad ridges or a pair of solder pad grooves. The solder pad ridges and the solder pad grooves filled with the solder or a resin can prevent the solder overflow problem.

Abstract translation: 防止衬底焊盘上的焊料溢出的封装结构包括多个管芯引脚，多个焊料和多个衬底焊盘。 模具销位于模具下方。 通过镀铜或蚀刻在衬底的上表面上形成衬底焊盘。 每个衬底焊盘具有至少一个焊盘连接点。 焊料将管芯引脚分别与相应的焊盘连接点相连。 每个焊盘连接点具有一对焊盘凸脊或一对焊盘凹槽。 焊料焊盘脊和填充有焊料或树脂的焊盘凹槽可以防止焊料溢出问题。

公开(公告)号：US20100094607A1

公开(公告)日：2010-04-15

申请号：US12653358

申请日：2009-12-11

Applicant: Glen C. Shepherd ,  Anthony Aaron Lynn Burton ,  Michael Ryan Ng ,  Mimi Munson Tantillo ,  Dieu-Huong Nguyen Tran

Inventor： Glen C. Shepherd ,  Anthony Aaron Lynn Burton ,  Michael Ryan Ng ,  Mimi Munson Tantillo ,  Dieu-Huong Nguyen Tran

IPC: G06F17/10 ,  H05K3/34 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K1/114 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/099 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: This invention relates to a substrate with via and pad structure(s) to reduce solder wicking. Each via and pad structure connects a component to conductive layers associated with the substrate. The substrate includes one or more plated vias, solder mask(s) surrounding the plated vias, and a conductive pad with a conductive trace connected to each plated via. The conductive pad extends beyond the terminal sides to increase solder formation and the solder mask reduces solder formation at the terminal end of the component. The via and pad structure is suitable for a variety of components and high component density. The invention also provides a computer implemented method for calculating the maximum distance of a conductive pad extending beyond the terminal side of a component.

Abstract translation: 本发明涉及一种具有通孔和衬垫结构以减少焊料芯吸的衬底。 每个通孔和焊盘结构将组件连接到与衬底相关联的导电层。 衬底包括一个或多个电镀通孔，围绕镀覆通孔的焊接掩模，以及具有连接到每个电镀通孔的导电迹线的导电焊盘。 导电焊盘延伸超过端子侧以增加焊料形成，并且焊接掩模减少部件终端处的焊料形成。 通孔和焊盘结构适用于各种组件和高组件密度。 本发明还提供一种用于计算延伸超过部件的端子侧的导电焊盘的最大距离的计算机实现的方法。

公开(公告)号：US20100065323A1

公开(公告)日：2010-03-18

申请号：US12622049

申请日：2009-11-19

Applicant: Yoichiro Kawamura ,  Shigeki Sawa ,  Katsuhiko Tanno ,  Hironori Tanaka ,  Naoaki Fujii

Inventor： Yoichiro Kawamura ,  Shigeki Sawa ,  Katsuhiko Tanno ,  Hironori Tanaka ,  Naoaki Fujii

IPC: H05K1/11

CPC classification number: H05K3/3478 ,  B23K3/0623 ,  B23K2101/42 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/544 ,  H01L24/81 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/3452 ,  H05K2201/0191 ,  H05K2201/099 ,  H05K2203/041 ,  H05K2203/0557 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed wiring board comprises a wiring substrate provided with at least one conductor circuit, a solder resist layer provided on the surface of the wiring substrate, at least one conductor pad formed from a part of the conductor circuit exposed from an opening provided in the solder resist layer, and at least one solder bump for mounting electronic parts on the conductor pad. In the printed wiring board, since the at least one conductor pad is aligned at a pitch of about 200 μm or less, and a ratio (W/D) of a diameter W of the solder bump to an opening diameter D of the opening formed in the solder resist layer is about 1.05 to about 1.7, connection reliability and insulation reliability can be easily improved.

Abstract translation: 一种印刷电路板，包括配置有至少一个导体电路的布线基板，设置在布线基板的表面上的阻焊层，至少一个导体焊盘，由导体电路的一部分露出， 抗蚀剂层和用于将电子部件安装在导体焊盘上的至少一个焊料凸块。 在印刷电路板中，由于至少一个导体焊盘以约200μm以下的间距排列，并且焊料凸块的直径W与形成的开口的开口直径D的比（W / D） 在阻焊层中约1.05〜约1.7，可以容易地提高连接可靠性和绝缘可靠性。

公开(公告)号：US20100022034A1

公开(公告)日：2010-01-28

申请号：US12220182

申请日：2008-07-22

Applicant: Joze Eura Antol ,  Kishor V. Desai ,  John William Osenbach ,  Brian Thomas Vaccaro

Inventor： Joze Eura Antol ,  Kishor V. Desai ,  John William Osenbach ,  Brian Thomas Vaccaro

IPC: H01L21/50

CPC classification number: H05K3/3452 ,  H05K3/3457 ,  H05K2201/099 ,  H05K2203/0271 ,  H05K2203/162

Abstract: Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.

公开(公告)号：US20090314538A1

公开(公告)日：2009-12-24

申请号：US12214700

申请日：2008-06-20

Applicant: Houssam Jomaa ,  Omar J. Bchir

Inventor： Houssam Jomaa ,  Omar J. Bchir

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/28 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5387 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1433 ,  H01L2924/15311 ,  H05K1/189 ,  H05K3/0035 ,  H05K3/3452 ,  H05K2201/0162 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/099 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2224/05599

Abstract: A microelectronic device mounting substrate includes a bond pad with a side wall and an upper surface. A dielectric first layer is disposed on the mounting substrate and a solder mask second layer is disposed on the dielectric first layer. A uniform recess is disposed through the solder mask second layer and the dielectric first layer that exposes the portion of the bond pad upper surface.

Abstract translation: 微电子器件安装基板包括具有侧壁和上表面的接合焊盘。 电介质第一层设置在安装基板上，并且焊料掩模第二层设置在电介质第一层上。 通过焊接掩模第二层和暴露接合焊盘上表面的部分的电介质第一层设置均匀的凹部。

公开(公告)号：US20090260854A1

公开(公告)日：2009-10-22

申请号：US12440556

申请日：2007-07-18

Applicant: Shingo Komura ,  Katsushige Akeyama ,  Motoo Yokoyama

Inventor： Shingo Komura ,  Katsushige Akeyama ,  Motoo Yokoyama

IPC: H05K1/00

CPC classification number: H05K3/3452 ,  H05K1/116 ,  H05K3/3468 ,  H05K2201/09381 ,  H05K2201/099 ,  H05K2203/044

Abstract: A resist opening 5a not covered with resist 4 around a through hole 2 provided through a board 1 is shaped so as to have a shape elongated in the direction of flow in flow soldering such that the surface tension acting on solder 6 upon the soldering is reduced.

Abstract translation: 通过板1设置的未被抗蚀剂4覆盖的通孔2的抗蚀剂开口5a成形为具有在流动焊接中沿流动方向延伸的形状，使得在焊接时作用在焊料6上的表面张力减小 。

公开(公告)号：US07598608B2

公开(公告)日：2009-10-06

申请号：US11736916

申请日：2007-04-18

Applicant: Yuji Kunimoto ,  Atsunori Kajiki

Inventor： Yuji Kunimoto ,  Atsunori Kajiki

IPC: H01L23/52

CPC classification number: H05K1/111 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/3452 ,  H05K2201/09227 ,  H05K2201/094 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: There is provided a mounting substrate on which a semiconductor chip is mounted using a flip chip bonding, having a plurality of connection pads which are connected to the semiconductor chip, and an insulation layer formed in such a manner as to cover the connection pads partially, wherein the insulation layer includes a first insulation layer which is formed in such a manner as to correspond to a center of the semiconductor chip and a second insulation layer which is formed in such a manner as to surround the first insulation layer, and wherein the plurality of connection pads include first connection pads which are partially covered by the first insulation layer and second connection pads which are partially covered by the second insulation layer.

Abstract translation: 提供一种安装基板，其上使用倒装芯片接合安装半导体芯片，其具有连接到半导体芯片的多个连接焊盘，以及以覆盖部分连接焊盘的方式形成的绝缘层， 其中所述绝缘层包括第一绝缘层，所述第一绝缘层以与所述半导体芯片的中心相对应的方式形成;以及第二绝缘层，所述第二绝缘层以围绕所述第一绝缘层的方式形成，并且其中所述多个 连接焊盘包括由第一绝缘层部分覆盖的第一连接焊盘和被第二绝缘层部分覆盖的第二连接焊盘。

公开(公告)号：US20090229863A1

公开(公告)日：2009-09-17

申请号：US12374123

申请日：2007-05-14

Applicant: Martin Fink ,  Georg Fischer

Inventor： Martin Fink ,  Georg Fischer

IPC: H05K1/09

CPC classification number: H05K1/118 ,  B60R16/0215 ,  H05K3/365 ,  H05K2201/09363 ,  H05K2201/09381 ,  H05K2201/099 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A conductor carrier includes a base insulating film, a contact insulating film, at least one first printed conductor and one second printed conductor. The contact insulating film includes at least one first recess and one second recess. The printed conductors are embedded between the two insulating films and each forms a first overlapping region with the first or second recess of the contact insulating film. The conductor carrier also includes an insulating region which separates the first printed conductor from the second printed conductor in an insulating manner due to the contact insulating film being less raised than outside the insulating region, and extends between the first and second recesses of the contact insulating film in a meandering manner. A configuration having the conductor carrier is also provided.

Abstract translation: 导体载体包括基底绝缘膜，接触绝缘膜，至少一个第一印刷导体和一个第二印刷导体。 接触绝缘膜包括至少一个第一凹部和一个第二凹部。 印刷的导体嵌入在两个绝缘膜之间，并且每个与接触绝缘膜的第一或第二凹部形成第一重叠区域。 导体载体还包括绝缘区域，其由于接触绝缘膜比绝缘区域外部稍微升高而以绝缘方式将第一印刷导体与第二印刷导体分离，并且在接触绝缘的第一和第二凹部之间延伸 电影以蜿蜒的方式。 还提供了具有导体载体的构造。