公开(公告)号：US07936567B2

公开(公告)日：2011-05-03

申请号：US12107971

申请日：2008-04-23

Applicant: Tsuneaki Takashima ,  Jun Otsuka ,  Makoto Origuchi ,  Yukinobu Nagao ,  Chy Narith ,  Kozo Yamasaki

Inventor： Tsuneaki Takashima ,  Jun Otsuka ,  Makoto Origuchi ,  Yukinobu Nagao ,  Chy Narith ,  Kozo Yamasaki

IPC: H05K1/18

CPC classification number: H05K1/0231 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for manufacturing a wiring board with built-in component. The method provides a secure connection between a component and interlayer insulating layers so that the wiring board with built-in component has excellent reliability. The wiring board is manufactured through a core board preparation step, a component preparation step, an accommodation step and a height alignment step. In the core board preparation step, a core board having an accommodation hole therein is prepared. In the component preparation step, a ceramic capacitor having therein a plurality of protruding conductors which protrudes from a capacitor rear surface is prepared. In the accommodation step, the ceramic capacitor is accommodated in the accommodation hole with the core rear surface facing the same side as the capacitor rear surface. In the height alignment step, a surface of a top portion of the protruding conductor and a surface of a conductor layer formed on the core rear surface are aligned to the same height.

Abstract translation: 一种内置元件制造布线板的方法。 该方法提供了组件和层间绝缘层之间的安全连接，使得具有内置部件的接线板具有优异的可靠性。 通过芯板制备步骤，组分制备步骤，调节步骤和高度对准步骤制造布线板。 在芯板制备步骤中，制备其中具有容纳孔的芯板。 在部件准备步骤中，制备了具有从电容器后表面突出的多个突出导体的陶瓷电容器。 在接合步骤中，陶瓷电容器容纳在容纳孔中，其中芯后表面与电容器后表面相同。 在高度对准步骤中，突出导体的顶部的表面和形成在芯部后表面上的导体层的表面被排列成相同的高度。

公开(公告)号：US20110083794A1

公开(公告)日：2011-04-14

申请号：US12951895

申请日：2010-11-22

Applicant: Motohiko Sato ,  Kazuhiro Hayashi ,  Kenji Murakami ,  Motonobu Kurahashi ,  Yusuke Kaieda ,  Jun Otsuka ,  Manabu Sato

Inventor： Motohiko Sato ,  Kazuhiro Hayashi ,  Kenji Murakami ,  Motonobu Kurahashi ,  Yusuke Kaieda ,  Jun Otsuka ,  Manabu Sato

IPC: B29C65/02

CPC classification number: H05K1/0231 ,  H01G4/228 ,  H01G4/30 ,  H01G4/38 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10712 ,  H01L2924/00

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract translation: 一种电容器，其具有电容器，所述电容器包括：电容器主体，包括多个电介质层和设置在所述不同电介质层之间的内部电极层，其中所述电容器本体在所述电容器主体的至少一个侧面中， 从所述电容器主体的第一主面和位于与所述第一主面相反的一侧的第二主面中的至少一个在所述电容器本体的厚度方向上延伸的凹部。

公开(公告)号：US07889509B2

公开(公告)日：2011-02-15

申请号：US11513039

申请日：2006-08-31

Applicant: Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

Inventor： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

IPC: H05K7/00

CPC classification number: H05K1/185 ,  H01G2/06 ,  H01G4/385 ,  H01L23/49816 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: A circuit board (10, 10″, 10′″) comprising: a board core (11) having a main core surface (12) and a rear core surface (13); a ceramic capacitor (101, 101′, 101″, 101′″, 101″″, 101″″′, 101″″″) having a main capacitor surface (102) and a rear capacitor surface (103), having a structure in which a first inner electrode layer (141) and a second inner electrode layer (142) are alternately stacked with a ceramic dielectric layer (105) interposed therebetween, and having a plurality of capacitor function units (107, 108) being electrically independent from each other, the ceramic capacitor (101, 101′, 101″, 101′″, 101″″, 101″″′, 101″″″) being buried in the board core (11) in a state where the main core surface (12) and the main capacitor surface (102) are directed in a same direction; and a buildup layer (31) having a structure in which an interlayer insulating layer (33, 35) and a conductor layer (42) are alternately stacked on the main core surface (12) and the main capacitor surface (102) and having a semiconductor integrated circuit device mounting region (23, 51, 52) for mounting a semiconductor integrated circuit device (21, 53, 54) having a plurality of processor cores (24, 25) on a surface (39) of the buildup layer (31), wherein the plurality of capacitor function units (107, 108) are capable of being electrically connected to the plurality of processor cores (24, 25), respectively.

Abstract translation: 一种电路板（10,10“，10”），包括：具有主芯表面（12）和后芯表面（13）的板芯（11）; 具有主电容器表面（102）和后电容器表面（103）的陶瓷电容器（101,101'，101“，101”，101“”，101“”，101“”“）， 其中第一内部电极层（141）和第二内部电极层（142）交替层叠有介于其间的陶瓷介电层（105），并且具有多个电容器功能单元（107,108），其电独立于 相互之间的陶瓷电容器（101,101'，101“，101”，101“，101”，101“”101“”）被埋在板芯11中， （12）和主电容器表面（102）指向相同的方向; 以及具有层间绝缘层（33,35）和导体层（42）在主芯面（12）和主电容器表面（102）上交替层叠的结构的积层（31），具有 半导体集成电路器件安装区域（23,51,52），用于安装具有多个处理器核心（24,25）的半导体集成电路器件（21,53,54），所述多个处理器核心（24,25）在所述生成层（31）的表面（39）上 ），其中所述多个电容器功能单元（107,108）能够分别电连接到所述多个处理器核（24,25）。

公开(公告)号：US20100163290A1

公开(公告)日：2010-07-01

申请号：US12606593

申请日：2009-10-27

Applicant: Hiroyasu Nagata

Inventor： Hiroyasu Nagata

IPC: H05K1/16 ,  H01B13/00 ,  B32B38/10

CPC classification number: B32B37/025 ,  B32B2038/0092 ,  B32B2309/02 ,  B32B2309/105 ,  B32B2309/12 ,  B32B2457/08 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/2518 ,  H05K1/0231 ,  H05K1/0269 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2201/10712 ,  H05K2203/166 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1052 ,  Y10T156/11 ,  Y10T156/1195

Abstract: A method for manufacturing printed wiring board including preparing an electronic component having first and second surfaces and electrode on the first surface, forming in an adhesive tape a mark, mounting based on the mark the component on the tape such that the second surface faces the adhesive of the tape, forming another mark on insulative substrate having first and second surfaces, forming in the substrate an opening larger than the component, mounting based on the marks the substrate on the tape such that the component is in the opening of the substrate, fixing the component to the substrate using resin, forming an insulation layer on the first surface of the substrate where the component is accommodated, removing the tape, forming in the layer an opening reaching the electrode, forming a conductive circuit on the layer, and forming in the opening of the layer a via connected to the electrode.

Abstract translation: 一种制造印刷线路板的方法，包括制备具有第一和第二表面的电子部件和在第一表面上的电极，在胶带上形成标记，基于将该部件标记在带上以使得第二表面面向粘合剂 的带，在具有第一和第二表面的绝缘基板上形成另一个标记，在基板上形成比部件大的开口，基于将基板标记在带上的安装，使得部件在基板的开口中，固定 使用树脂的基板上的部件，在容纳部件的基板的第一表面上形成绝缘层，去除带，在该层中形成到达电极的开口，在该层上形成导电电路，并形成 打开连接到电极的层a通孔。

公开(公告)号：US20090266594A1

公开(公告)日：2009-10-29

申请号：US12189852

申请日：2008-08-12

Applicant: Kazuhiro Yoshikawa

Inventor： Kazuhiro Yoshikawa

IPC: H05K1/16 ,  H01B13/00

CPC classification number: H05K1/162 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3511 ,  H05K1/113 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/09718 ,  H05K2201/10515 ,  H05K2201/10712

Abstract: A wiring substrate and method of forming a wiring substrate. The wiring substrate includes a base substrate, a first resin insulating layer provided on the base substrate and a laminated capacitor formed within the first resin insulating layer. The laminated capacitor includes a plurality of capacitors laminated to each other by adhesive, each capacitor including a first electrode, a second electrode opposing the first electrode and a dielectric layer interposed between the first and second electrodes. A first via conductor electrically connects the first electrodes of the plurality of capacitors to each other, and a second via conductor electrically connects the second electrodes of the plurality of capacitors to each other. A first external terminal electrically connects to the first via conductor, and a second external terminal electrically connects to the second via conductor.

Abstract translation: 布线基板以及布线基板的形成方法。 布线基板包括基底基板，设置在基底基板上的第一树脂绝缘层和形成在第一树脂绝缘层内的叠层电容器。 层叠电容器包括通过粘合剂彼此层叠的多个电容器，每个电容器包括第一电极，与第一电极相对的第二电极和介于第一和第二电极之间的电介质层。 第一通孔导体将多个电容器的第一电极彼此电连接，并且第二通孔导体将多个电容器的第二电极彼此电连接。 第一外部端子电连接到第一通孔导体，第二外部端子电连接到第二通孔导体。

公开(公告)号：US07532453B2

公开(公告)日：2009-05-12

申请号：US11601760

申请日：2006-11-20

Applicant: Hiroshi Yamamoto ,  Toshitake Seki ,  Yasuhiko Inui ,  Jun Otsuka ,  Manabu Sato

Inventor： Hiroshi Yamamoto ,  Toshitake Seki ,  Yasuhiko Inui ,  Jun Otsuka ,  Manabu Sato

IPC: H01G4/228

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: In order to provide a built-in capacitor type wiring board capable of preventing misalignment of the capacitor, a capacitor built-in type wiring board is provided which includes a core board; a multilayer portion disposed on at least one side of the core board and formed by a plurality of interlayer insulating layers; and a plurality of conductor layers alternately laminated on the core board. The capacitor is of a chip-like shape with first and second main surfaces and includes a dielectric layer; electrode layers laminated on the dielectric layer; and a hole portion opening at least at the second main surface. The capacitor is embedded in the interlayer insulating layers so that the second main surface faces the core board.

Abstract translation: 为了提供能够防止电容器未对准的内置电容器型布线板，提供了一种电容器内置型布线板，其包括芯板; 多层部分，设置在所述芯板的至少一侧上，并由多个层间绝缘层形成; 以及在芯板上交替层叠的多个导体层。 电容器是具有第一和第二主表面的芯片状形状并且包括电介质层; 层压在电介质层上的电极层; 以及至少在所述第二主表面处开口的孔部分。 电容器嵌入在层间绝缘层中，使得第二主表面面向芯板。

公开(公告)号：US20080142961A1

公开(公告)日：2008-06-19

申请号：US11611063

申请日：2006-12-14

Applicant: Christopher C. Jones ,  David Bach ,  Timothe Litt ,  Larry Binder ,  Kaladhar Radhakrishnan ,  Cengiz A. Palanduz

Inventor： Christopher C. Jones ,  David Bach ,  Timothe Litt ,  Larry Binder ,  Kaladhar Radhakrishnan ,  Cengiz A. Palanduz

IPC: H01L23/34

CPC classification number: H05K1/0231 ,  H01L25/0655 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/145 ,  H05K1/183 ,  H05K2201/10515 ,  H05K2201/10712 ,  H05K2201/10734

Abstract: A ceramic package substrate has a recess. This allows a device in that recess to be close to a die attached to the substrate's top side, for better performance. The device may be an array capacitor, an in-silicon voltage regulator, or another device or devices.

Abstract translation: 陶瓷封装基板具有凹部。 这使得该凹部中的器件靠近附接到衬底顶侧的管芯，以获得更好的性能。 该器件可以是阵列电容器，硅内电压调节器或其它器件。

公开(公告)号：US20070117338A1

公开(公告)日：2007-05-24

申请号：US11603161

申请日：2006-11-22

Applicant: Hiroshi Yamamoto ,  Toshitake Seki ,  Jun Otsuka ,  Manabu Sato ,  Masahiko Okuyama

Inventor： Hiroshi Yamamoto ,  Toshitake Seki ,  Jun Otsuka ,  Manabu Sato ,  Masahiko Okuyama

IPC: H01L21/20 ,  H01L29/00

CPC classification number: H05K1/186 ,  H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00

Abstract: A via array capacitor comprising: a capacitor body including a first main surface and a second main surface and having a structure in which dielectric layers and inner electrode layers are alternately laminated; a plurality of via conductors which conduct the inner electrode layers to each other and are, as a whole, arranged in array form; and metal-containing layers which are disposed on at least one of the first main surface and the second main surface, wherein a total of a thickness of the metal-containing layers disposed on the first main surface and a thickness of the metal-containing layers disposed on the second main surface is from 15% to 80% of an overall thickness of the via array capacitor.

Abstract translation: 一种通孔阵列电容器，包括：电容器主体，包括第一主表面和第二主表面，并且具有交替层叠电介质层和内电极层的结构; 多个通孔导体，其将内部电极层彼此导引并且整体上排列成阵列形式; 和设置在第一主表面和第二主表面中的至少一个上的含金属层，其中设置在第一主表面上的含金属层的厚度和含金属层的厚度的总和 设置在第二主表面上的通孔阵列电容器的总厚度的15％至80％。

公开(公告)号：US20070030628A1

公开(公告)日：2007-02-08

申请号：US11498785

申请日：2006-08-04

Applicant: Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

Inventor： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

IPC: H01G4/06

CPC classification number: H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

Abstract translation: 一种电容器，包括：电容器主体，包括多个叠层电介质层，多个内部电极层，分别设置在相互相邻的电介质层之间，第一主表面位于电介质层的层叠方向上， 第二主表面与第一主表面相对; 第一外电极，形成在所述电容器主体的所述第一主表面上并电连接到所述内电极层; 形成在所述电容器主体的所述第二主表面上并与内部电极层电连接的第二外部电极; 形成在所述电容器主体的所述第一主表面上的第一虚拟电极; 以及形成在电容器主体的第二主表面上的第二虚拟电极。

公开(公告)号：US20050207091A1

公开(公告)日：2005-09-22

申请号：US11126157

申请日：2005-05-11

Applicant: Rokuro Kambe ,  Yukihiro Kimura ,  Yasuhiro Sugimoto ,  Kazuhiro Suzuki

Inventor： Rokuro Kambe ,  Yukihiro Kimura ,  Yasuhiro Sugimoto ,  Kazuhiro Suzuki

IPC: H01L23/12 ,  H01G4/228 ,  H01L23/498 ,  H01L23/50 ,  H01L27/01 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

CPC classification number: H05K1/0231 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/50 ,  H01L27/016 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: An intermediate substrate includes a substrate core formed by a main core body portion constructed of a sheet of polymer material and having a subsidiary core accommodation portion formed therein. A ceramic subsidiary core portion, which is constructed of a ceramic sheet, is accommodated in the subsidiary core accommodation portion and is of a thickness matching that of the main core body portion. A thin film capacitor is formed on a first main surface side of a plate-like base of the core portion and includes first and second thin film electrodes separated from each other by a thin film dielectric layer so as to provide direct current isolation between the electrodes. First and second direct current isolated terminals of a first terminal array are electrically connected to the first and second thin film electrodes.

Abstract translation: 中间基板包括由主体芯体部分形成的基体芯部，所述主芯体部分由聚合物材料片构成并且具有形成在其中的副芯部容纳部分。 由陶瓷片构成的陶瓷副芯部被容纳在副芯容纳部中，其厚度与主芯体部的厚度一致。 在芯部的板状基体的第一主面侧形成薄膜电容器，并且包括通过薄膜电介质层彼此分离的第一和第二薄膜电极，以在电极之间提供直流隔离 。 第一端子阵列的第一和第二直流隔离端子电连接到第一和第二薄膜电极。