公开(公告)号：US20060118972A1

公开(公告)日：2006-06-08

申请号：US11339973

申请日：2006-01-26

申请人： Seung-Duk Baek ,  In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Young-Hee Song ,  Myeong-Soon Park

发明人： Seung-Duk Baek ,  In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Young-Hee Song ,  Myeong-Soon Park

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00

摘要： Packaged integrated circuit devices include a package substrate and a multi-chip stack of integrated circuit devices on the package substrate. The multi-chip stack includes at least one chip-select rerouting conductor. This rerouting conductor extends from the package substrate to a chip pad on an upper one of the chips in the multi-chip stack. The chip-select rerouting conductor extends through a first via hole in a lower one of the chips in the multi-chip stack.

公开(公告)号：US20060060970A1

公开(公告)日：2006-03-23

申请号：US11195361

申请日：2005-08-01

申请人： Se-Young Jeong ,  Sung-Min Sim ,  Soon-Bum Kim ,  In-Young Lee ,  Young-Hee Song

发明人： Se-Young Jeong ,  Sung-Min Sim ,  Soon-Bum Kim ,  In-Young Lee ,  Young-Hee Song

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.

摘要翻译： 互连结构包括具有内部电路的集成电路（IC）芯片和用于将内部电路电连接到外部电路的端子，设置在IC芯片的顶表面上的钝化层，钝化层被配置为保护内部电路 以及使所述终端暴露于所述I / O焊盘包括与所述端子接触的第一部分和在所述钝化层上延伸的第二部分的输入/输出（I / O）焊盘，以及设置在所述钝化层上的无电镀层 I / O板。

公开(公告)号：US20060019467A1

公开(公告)日：2006-01-26

申请号：US11147677

申请日：2005-06-08

申请人： In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Young-Hee Song ,  Myeong-Soon Park

发明人： In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Young-Hee Song ,  Myeong-Soon Park

IPC分类号： H01L21/78

CPC分类号： H01L23/481 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00

摘要： Methods of forming integrated circuit chips include forming a plurality of criss-crossing grooves in a semiconductor wafer having a plurality of contact pads thereon and filling the criss-crossing grooves with an electrically insulating layer. The electrically insulating layer is then patterned to define at least first and second through-holes therein that extend in a first one of the criss-crossing groves. The first and second through-holes are then filled with first and second through-chip connection electrodes, respectively. The semiconductor wafer is then diced into a plurality of integrated circuit chips by cutting through the electrically insulating layer in a criss-crossing pattern that overlaps with the locations of the criss-crossing grooves.

摘要翻译： 形成集成电路芯片的方法包括在其上具有多个接触焊盘的半导体晶片中形成多个交叉交叉的沟槽，并用电绝缘层填充交叉沟槽。 然后对电绝缘层进行图案化以在其中限定至少第一和第二通孔，该第一和第二通孔在第一个十字交叉的树丛中延伸。 然后分别用第一和第二贯通芯片连接电极填充第一和第二通孔。 然后通过与交叉交叉的沟槽的位置重叠的交叉图案切割电绝缘层，将半导体晶片切割成多个集成电路芯片。

公开(公告)号：US20180030578A1

公开(公告)日：2018-02-01

申请号：US15553688

申请日：2016-02-24

申请人： In-Young LEE

发明人： In-Young LEE ,  Kang-Hyung KIM ,  Hyun-Seok JEON

IPC分类号： C22C23/04 ,  C22C1/02

摘要： Disclosed is a magnesium alloy that has high thermal conductivity and flame retardancy and facilitates plastic working, wherein magnesium is added with 0.5 to 5 wt % of zinc (Zn) and 0.3 to 2.0 wt % of at least one of yttrium (Y) and mischmetal, with, as necessary, 1.0 wt % or less of at least one selected from among calcium (Ca), silicon (Si), manganese (Mn) and tin (Sn), the total amount of alloy elements being 2.5 to 6 wt %. A method of manufacturing the same is also provided, including preparing a magnesium-zinc alloy melt in a melting furnace, adding high-melting-point elements in the form of a master alloy and melting them, and performing mechanical stirring during cooling of a cast material in a continuous casting mold containing the magnesium alloy melt, thus producing a magnesium alloy cast material having low segregation, after which a chill is removed from the cast material or diffusion annealing is performed, followed by molding through a tempering process such as rolling, extrusion or forging. This magnesium alloy is improved in ductility by the action of alloy elements for inhibiting the formation of lamella precipitates due to a low-melting-point eutectic phase in a magnesium matrix structure, can be extruded even at a pressure of 1,000 kgf/cm2 or less due to the increased plasticity thereof, and can exhibit thermal conductivity of 100 W/m·K or more and flame retardancy satisfying the requirements for aircraft materials and is thus suitable for use in fields requiring fire safety, thereby realizing wide application thereof as a heat sink or a structural material for portable appliances, vehicles and aircraft components and contributing to weight reduction.

公开(公告)号：US08482129B2

公开(公告)日：2013-07-09

申请号：US13027594

申请日：2011-02-15

申请人： In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

发明人： In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2224/05552

摘要： A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.

摘要翻译： 一种制造半导体器件的方法包括在半导体晶片上形成集成电路区域。 在集成电路区域上形成第一金属层图案。 通孔形成为延伸穿过第一金属层图案和集成电路区域。 最终的金属层图案形成在第一金属层图案之上并且在通孔内。 在通孔内形成插头。 此后，形成钝化层以覆盖最终金属层图案。

公开(公告)号：US08415804B2

公开(公告)日：2013-04-09

申请号：US12639241

申请日：2009-12-16

申请人： Ho-jin Lee ,  Dong-hyun Jang ,  In-young Lee ,  Min-seung Yoon ,  Son-kwan Hwang

发明人： Ho-jin Lee ,  Dong-hyun Jang ,  In-young Lee ,  Min-seung Yoon ,  Son-kwan Hwang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

CPC分类号： H01L24/13 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29298 ,  H01L2224/83194 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/05552

摘要： A semiconductor chip, a method of fabricating the same, and a stack module and a memory card including the semiconductor chip include a first surface and a second surface facing the first surface is provided. At least one via hole including a first portion extending in a direction from the first surface of the substrate to the second surface of the substrate and a second portion that is connected to the first portion and has a tapered shape. At least one via electrode filling the at least one via hole is provided.

摘要翻译： 提供一种半导体芯片及其制造方法，以及包括半导体芯片的堆叠模块和存储卡，其包括第一表面和面对第一表面的第二表面。 至少一个通孔，包括在从基板的第一表面到基板的第二表面的方向上延伸的第一部分和连接到第一部分并具有锥形形状的第二部分。 提供至少一个填充至少一个通孔的通孔电极。

公开(公告)号：US08026235B1

公开(公告)日：2011-09-27

申请号：US12909513

申请日：2010-10-21

申请人： Ji Duck Kim ,  Hong-Chul Yoon ,  In Woo Kim ,  Min Jae Cho ,  In Young Lee ,  Sang Ho Lee ,  Eun Kyung Park ,  Kwon Jo Lim ,  Sang Hyun Nam

发明人： Ji Duck Kim ,  Hong-Chul Yoon ,  In Woo Kim ,  Min Jae Cho ,  In Young Lee ,  Sang Ho Lee ,  Eun Kyung Park ,  Kwon Jo Lim ,  Sang Hyun Nam

IPC分类号： C07D413/14 ,  A61K31/538

CPC分类号： C07D413/14

摘要： Discloses is a benzoxazine benzimidazole derivative, represented by Chemical Formula 1, functioning as an antagonist to the vanilloid receptor-1, a pharmaceutical composition comprising the same, and the use thereof. The benzoxazine benzimidazole derivative can be useful for preventing or treating a disease associated with antagonistic activity of vanilloid receptor-1, without hyperthermia: wherein, R1, R2, R3, R4 and R5 are as defined in the specification.

摘要翻译： 公开了用作对香草素受体-1的拮抗剂的化学式1表示的苯并恶嗪苯并咪唑衍生物，包含它们的药物组合物及其用途。 苯并恶嗪苯并咪唑衍生物可用于预防或治疗与没有高热的香草素受体-1的拮抗活性相关的疾病：其中，R1，R2，R3，R4和R5如说明书中所定义。

公开(公告)号：US07943544B2

公开(公告)日：2011-05-17

申请号：US12007746

申请日：2008-01-15

申请人： In-Young Lee ,  Jung-Bin Lee ,  Dong-Wha Kim

发明人： In-Young Lee ,  Jung-Bin Lee ,  Dong-Wha Kim

IPC分类号： B01J38/02

CPC分类号： B01J23/92 ,  B01J21/20 ,  B01J38/48 ,  B01J38/60 ,  B01J38/62 ,  Y10S502/514 ,  Y10S502/515 ,  Y10T436/22

摘要： The present invention provides a method of recycling a spent flue gas denitration catalyst and a method of determining a washing time of the spent flue gas denitration catalyst. The method of recycling the spent flue gas denitration catalyst includes physically removing solids deposited in the spent flue gas denitration catalyst, removing poisoning substances deposited in the spent flue gas denitration catalyst by washing the spent flue gas denitration catalyst with a washing liquid for a washing time determined by measuring the hydrogen ion concentration of the washing liquid and drying the resulting spent flue gas denitration catalyst.

摘要翻译： 本发明提供了废废气脱硝催化剂的再循环方法和废烟气脱硝催化剂的洗涤时间的测定方法。 废弃废气脱硝催化剂的再循环方法包括物理去除废烟道气脱硝催化剂中沉积的固体，通过用洗涤液洗涤废烟道脱硝催化剂洗涤废废气脱硝催化剂中的中毒物质，洗涤时间 通过测量洗涤液的氢离子浓度和干燥所得到的废烟气脱硝催化剂来测定。

公开(公告)号：US20100090338A1

公开(公告)日：2010-04-15

申请号：US12393109

申请日：2009-02-26

申请人： Ho Jin Lee ,  Dong Hyeon Jang ,  Nam Seog Kim ,  In Young Lee ,  Ha Young Yim

发明人： Ho Jin Lee ,  Dong Hyeon Jang ,  Nam Seog Kim ,  In Young Lee ,  Ha Young Yim

IPC分类号： H01L23/522 ,  H01L25/11 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01055 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941

摘要： A microelectronic structure includes a conductive pad on a substrate. The conductive pad includes first and second openings extending therethrough. A first conductive via on the conductive pad extends through the first opening in the conductive pad into the substrate. A second conductive via on the conductive pad adjacent the first conductive via extends through the second opening in the conductive pad into the substrate. At least one of the conductive vias may be electrically isolated from the conductive pad. Related devices and fabrication methods are also discussed.

摘要翻译： 微电子结构包括在衬底上的导电焊盘。 导电垫包括延伸穿过其中的第一和第二开口。 导电焊盘上的第一导电通孔延伸穿过导电焊盘中的第一开口进入衬底。 邻近第一导电通孔的导电焊盘上的第二导电通孔延伸穿过导电焊盘中的第二开口进入衬底。 导电通孔中的至少一个可以与导电焊盘电绝缘。 还讨论了相关设备和制造方法。

公开(公告)号：US20090215229A1

公开(公告)日：2009-08-27

申请号：US12385946

申请日：2009-04-24

申请人： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

发明人： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

IPC分类号： H01L21/50

CPC分类号： H01L23/3128 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening.