公开(公告)号：US09698269B2

公开(公告)日：2017-07-04

申请号：US15059793

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hua Tong ,  Tien-Ying Luo ,  Yan Ping Shen ,  Feng Zhou ,  Jun Lian ,  Haoran Shi ,  Min-hwa Chi ,  Jin Ping Liu ,  Haiting Wang ,  Seung Kim

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/324 ,  H01L21/02 ,  H01L21/321 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

公开(公告)号：US09691497B2

公开(公告)日：2017-06-27

申请号：US14867331

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Min-hwa Chi ,  Ajey P. Jacob

IPC: G11C17/16 ,  H01L23/525 ,  H01L29/78 ,  H01L29/06

CPC classification number: G11C17/16 ,  H01L23/5256 ,  H01L29/0673 ,  H01L29/785

Abstract: Programmable devices and fabrication methods thereof are presented. The programmable devices include, for instance, a first electrode and a second electrode electrically connected by a link portion. The link portion includes one material of a metal material or a semiconductor material and the first and second electrodes includes the other material of the metal material or the semiconductor material. For example, the link portion facilitates programming the programmable device by applying a programming current between the first electrode and the second electrode to facilitate migration of the one material of the link portion towards at least one of the first or second electrodes. In one embodiment, the programming current is configured to heat the link portion to facilitate the migration of the one material of the link portion towards the at least one of the first or second electrodes.

公开(公告)号：US09536991B1

公开(公告)日：2017-01-03

申请号：US15067435

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Min-hwa Chi

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L29/6681 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653

Abstract: A method of forming a single diffusion break includes patterning a fin hardmask disposed over a substrate. First and second fin arrays separated by an isolation region are etched into the substrate from the patterned fin hardmask. Any remaining fin hardmask being self-aligned with the fins. A first dielectric fill material is disposed and planarized over the arrays to expose top surfaces of the remaining fin hardmask. A second dielectric strip is formed over the first dielectric fill material to cover the isolation region and end portions of the remaining fin hardmask. Any exposed portions of the remaining fin hardmask are anisotropically etched away. The end portions of the remaining fin hardmask form base extensions of a base for a single diffusion break (SDB) in the isolation region. The first dielectric fill material and second dielectric strip are etched to complete formation of the base for the single diffusion break.

Abstract translation: 形成单个扩散断裂的方法包括图案化设置在基板上的散热片硬掩模。 由分离区隔开的第一和第二鳍状阵列从图案化的翅片硬掩模中蚀刻到基底中。 任何剩余的散热片硬掩模与翅片自对准。 第一介电填充材料在阵列上布置和平坦化以暴露剩余的散热片硬掩模的顶表面。 在第一介电填充材料上形成第二介质条以覆盖剩余的散热片硬掩模的隔离区域和端部。 剩余散热片硬掩模的任何暴露部分被各向异性地蚀刻掉。 剩余散热片硬掩模的端部形成用于隔离区域中的单个扩散断裂（SDB）的基部的基部延伸部。 蚀刻第一介电填充材料和第二介电条以完成单扩散断裂的基底的形成。

公开(公告)号：US09524911B1

公开(公告)日：2016-12-20

申请号：US14858412

申请日：2015-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hao-Cheng Tsai ,  Yong Meng Lee ,  Min-hwa Chi

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/40 ,  H01L27/088 ,  H01L21/762

CPC classification number: H01L21/823481 ,  H01L21/76232 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods for creating self-aligned FINFET SDBs for minimum gate junction pitch and epitaxy formation. Embodiments include forming separated openings in a hard mask on upper surfaces of Si fins; forming cavities in the fins, each of the cavities having a concave shape and a width extending under the hard mask on each side of the cavity; forming trenches in the fins, the trenches having an upper width substantially equal to a width of the openings and less than the width of a cavity; removing the hard mask; filling the trenches and the cavities with oxide, forming STI regions; forming an oxide mask layer on the upper surfaces of the fins and the STI regions; removing upper portions of the oxide in sections between the STI regions; and removing remaining portions of the oxide mask revealing the fins and upper surfaces of the STI regions.

Abstract translation: 用于创建自对准FINFET SDB的方法，用于最小栅极连接节距和外延形成。 实施例包括在Si散热片的上表面上形成硬掩模中的分开的开口; 在所述翅片中形成空腔，所述空腔中的每一个具有凹形形状和在所述空腔的每一侧上在所述硬掩模下方延伸的宽度; 在所述翅片中形成沟槽，所述沟槽的上宽度基本上等于所述开口的宽度并小于空腔的宽度; 去除硬面膜; 用氧化物填充沟槽和空腔，形成STI区域; 在鳍片和STI区域的上表面上形成氧化物掩模层; 去除STI区域之间部分氧化物的上部; 并且去除暴露出STI区域的翅片和上表面的氧化物掩模的剩余部分。

公开(公告)号：US09508795B2

公开(公告)日：2016-11-29

申请号：US14613983

申请日：2015-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Min-hwa Chi ,  Ashish Baraskar ,  Jagar Singh

IPC: H01L21/20 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/31116 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/78696

Abstract: Methods are presented for fabricating nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate and forming a fin above the substrate so that the fin has a first sidewall including one or more elongate first sidewall protrusions and a second sidewall including one or more elongate second sidewall protrusions, with the one or more elongate second sidewall protrusions being substantially aligned with the one or more elongate first sidewall protrusions; and, anisotropically etching the fin with the elongate first sidewall protrusions and the elongate second sidewall protrusions to define the one or more nanowires. The etchant may be chosen to selectively etch along a pre-defined crystallographic plane, such as the (111) crystallographic plane, to form the nanowire structures.

Abstract translation: 提出了用于制造纳米线结构的方法，例如一个或多个纳米线场效应晶体管。 所述方法包括例如：提供衬底并在衬底上形成翅片，使得翅片具有包括一个或多个细长的第一侧壁突出部的第一侧壁和包括一个或多个细长的第二侧壁突出部的第二侧壁， 更细长的第二侧壁突起基本上与一个或多个细长的第一侧壁突起对准; 并且用细长的第一侧壁突起和细长的第二侧壁突起各向异性地蚀刻翅片以限定一个或多个纳米线。 可以选择蚀刻剂以沿着预定义的结晶平面（例如（111）晶面）选择性地蚀刻，以形成纳米线结构。

公开(公告)号：US09502301B2

公开(公告)日：2016-11-22

申请号：US14730614

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Min-hwa Chi

IPC: H01L21/82 ,  H01L21/285 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/283 ,  H01L21/324 ,  H01L21/225

CPC classification number: H01L21/823443 ,  H01L21/2253 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76889 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823835 ,  H01L21/823842

Abstract: Methods are provided for fabricating multi-layer semiconductor structures. The methods include, for example: providing a first layer and a second layer over a substrate, the first layer including a first metal and the second layer including a second metal, where the second layer is disposed over the first layer and the first metal and second metal are different metals; and annealing the first layer, the second layer, and the substrate to react at least a portion of the first metal of the first layer to form a first reacted layer and at least a portion of the second metal of the second layer to form a second reacted layer, where at least one of the first reacted layer or the second reacted layer includes at least one of a first metal silicide of the first metal or a second metal silicide of the second metal.

Abstract translation: 提供了制造多层半导体结构的方法。 所述方法包括例如：在衬底上提供第一层和第二层，第一层包括第一金属，第二层包括第二金属，其中第二层设置在第一层和第一金属之上， 第二种金属是不同的金属; 以及退火所述第一层，所述第二层和所述衬底以使所述第一层的所述第一金属的至少一部分反应以形成第一反应层和所述第二层的所述第二金属的至少一部分，以形成第二层 其中第一反应层或第二反应层中的至少一个包含第一金属的第一金属硅化物或第二金属的第二金属硅化物中的至少一种。

公开(公告)号：US09425100B1

公开(公告)日：2016-08-23

申请号：US14694276

申请日：2015-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhaoxu Shen ,  Min-hwa Chi ,  Haiting Wang ,  Qin Wang ,  Meixiong Zhao ,  Duohui Bei

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/306 ,  H01L29/06 ,  H01L29/10 ,  H01L21/308

CPC classification number: H01L21/823412 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: Methods and transistors for circuit structures are provided. The methods include, for instance: defining a channel region in a substrate, the channel region having at least one channel region sidewall adjoining an isolation material; recessing the isolation material to expose an upper portion of the at least one channel region sidewall; and providing a gate structure over a gate interface area with the channel region. The gate interface area includes at least the upper portion of the at least one channel region sidewall and an upper surface of the channel region so that a threshold voltage of the gate structure may be reduced. The methods may also include etching an elongate notch in the upper portion of the at least one channel region sidewall to increase a size of the gate interface area and further reduce the threshold voltage of the gate structure.

Abstract translation: 提供了用于电路结构的方法和晶体管。 所述方法包括例如：在衬底中限定沟道区，所述沟道区具有邻近隔离材料的至少一个沟道区侧壁; 使隔离材料凹陷以暴露至少一个通道区域侧壁的上部; 以及在与沟道区域的栅极接口区域上提供栅极结构。 栅极界面区域至少包括至少一个沟道区域侧壁的上部和沟道区域的上表面，使得可以减小栅极结构的阈值电压。 所述方法还可以包括蚀刻在所述至少一个沟道区域侧壁的上部中的细长凹口以增加栅极界面面积的尺寸并进一步降低栅极结构的阈值电压。

公开(公告)号：US09385124B1

公开(公告)日：2016-07-05

申请号：US14845499

申请日：2015-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen Pin Peng ,  Min-hwa Chi ,  Garo Jacques Derderian

IPC: H01L21/336 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L27/092 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: One method disclosed herein includes, among other things, forming a first spacer proximate gate structures of first and second transistors that are opposite type transistors, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, performing a timed, wet etching process on both of the transistors so as to completely remove the layer of second spacer material from the second transistor while leaving a reduced thickness second spacer positioned adjacent the first spacer of the first transistor, wherein the reduced thickness second spacer has a thickness that is less than an initial thickness of the initial second spacer, and forming a third spacer on and in contact with the first spacer of the second transistor.

Abstract translation: 本文公开的一种方法包括形成与第一和第二晶体管相对的第一和第二晶体管的栅极结构的第一间隔区，与第一晶体管相反，形成靠近第一晶体管的第一间隔物的初始第二间隔区， 第二晶体管，对两个晶体管执行定时湿式蚀刻处理，以便从第二晶体管完全去除第二间隔物材料层，同时留下邻近第一晶体管的第一间隔物定位的减小厚度的第二间隔物，其中减少 厚度第二间隔物的厚度小于初始第二间隔物的初始厚度，并且在第二晶体管的第一间隔物上形成第三间隔物并与第二间隔物接触。

公开(公告)号：US09362277B2

公开(公告)日：2016-06-07

申请号：US14175827

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Ajey Jacob ,  Abhijeet Paul

IPC: H01L21/8238 ,  H01L21/205 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Abstract translation: 公开了一种形成具有小占地面积的多值逻辑晶体管的方法和所得到的器件。 实施例包括在硅衬底上形成多个翅片，每个翅片用硬掩模覆盖; 用氧化物填充翅片和硬掩模之间的空间; 去除硬掩模并使每个翅片凹陷，在每个翅片上的氧化物中形成空腔; 在每个空腔中形成多个Si基层，其中Ge或C的百分比增加或掺杂剂浓度从底层到顶层的浓度降低; 执行CMP以平坦化到翅片的顶部; 将氧化物凹陷到具有等于每个Si基层的厚度的厚度的略微低于翅片顶部的深度; 以及在多个Si基层上形成高k栅极电介质和金属栅电极。

公开(公告)号：US20150016174A1

公开(公告)日：2015-01-15

申请号：US13937962

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L27/112 ,  G11C17/16 ,  H01L21/768

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L21/76816 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus are provided for an integrated circuit with a programmable electrical connection. The apparatus includes an inactive area with a memory line passing over the inactive area. The memory line includes a programmable layer. An interlayer dielectric is positioned over the memory line and the inactive area, and an extending member extends through the interlayer dielectric. The extending member is electrically connected to the programmable layer of the memory line at a point above the inactive area.

Abstract translation: 为具有可编程电气连接的集成电路提供了方法和装置。 该装置包括具有通过非活动区域的存储器线路的无效区域。 存储线包括可编程层。 层间电介质位于存储器线路和无源区域之上，并且延伸部件延伸穿过层间电介质。 延伸构件在非活动区域上方的点处电连接到存储器线路的可编程层。