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    N-FET with a highly doped source/drain and strain booster
    67.
    发明授权
    N-FET with a highly doped source/drain and strain booster 有权
    具有高掺杂源/漏极和应变增强器的N-FET

    公开(公告)号：US08247285B2

    公开(公告)日：2012-08-21

    申请号：US12341674

    申请日：2008-12-22

    Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

    Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

    IPC: H01L21/8238

    CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L21/28255 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/7833

    Abstract: A structure and method of making an N-FET with a highly doped source/drain and strain booster are presented. The method provides a substrate with a Ge channel region. A gate dielectric is formed over the Ge channel and a gate electrode is formed over the gate dielectric. Sacrificial gate spacers are disposed on the sidewalls of the gate dielectric and gate electrode. Cavities are etched into the substrate extending under the sacrificial gate spacers. Si1-xGex source/drain regions are doped in-situ during formation, x

    Abstract translation: 提出了制造具有高掺杂源/漏和应变增强器的N-FET的结构和方法。 该方法提供具有Ge沟道区的衬底。 在Ge沟道上方形成栅极电介质，在栅极电介质上形成栅电极。 牺牲栅间隔件设置在栅极电介质和栅电极的侧壁上。 凹坑被蚀刻到在牺牲栅极间隔物下面延伸的衬底中。 Si1-xGex源/漏区在形成期间原位掺杂，x <0.85。

    Depletion-free MOS using atomic-layer doping
    69.
    发明授权
    Depletion-free MOS using atomic-layer doping 有权
    使用原子层掺杂的无耗氧MOS

    公开(公告)号：US07790535B2

    公开(公告)日：2010-09-07

    申请号：US12211546

    申请日：2008-09-16

    Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

    Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

    IPC: H01L21/20

    CPC classification number: H01L21/823842 ,  H01L21/2254 ,  H01L21/28035 ,  H01L29/4925 ,  H01L29/6659

    Abstract: A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.

    Abstract translation: 提供半导体器件和制造方法。 介电层形成在衬底上，并且在介电层上形成未掺杂的第一含硅层。 原子层掺杂用于掺杂未掺杂的含硅层。 在第一含硅层上形成第二含硅层。 该过程可以扩展到包括在同一晶片上形成PMOS和NMOS器件。 例如，在原子层掺杂之前，第一含硅层可以在PMOS区中减薄。 在NMOS区域中，去除第一含硅层的掺杂部分，使得NMOS中的第一含硅层的剩余部分未掺杂。 此后，可以使用另一种原子层掺杂工艺将NMOS区域中的第一含硅层掺杂到不同的导电类型。 可以形成掺杂到相应导电类型的第三含硅层。

    Methods for Forming NMOS and PMOS Devices on Germanium-Based Substrates
    70.
    发明申请
    Methods for Forming NMOS and PMOS Devices on Germanium-Based Substrates 审中-公开
    在锗基底板上形成NMOS和PMOS器件的方法

    公开(公告)号：US20100181626A1

    公开(公告)日：2010-07-22

    申请号：US12617026

    申请日：2009-11-12

    Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

    Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

    IPC: H01L27/092

    CPC classification number: H01L21/823807 ,  H01L21/823412 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

    Abstract: A semiconductor structure includes a germanium substrate having a first region and a second region. A first silicon cap is over the first region of the germanium substrate. A second silicon cap is over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap. A PMOS device includes a first gate dielectric over the first silicon cap. An NMOS device includes a second gate dielectric over the second silicon cap.

    Abstract translation: 半导体结构包括具有第一区域和第二区域的锗衬底。 第一硅帽位于锗衬底的第一区域之上。 第二硅帽位于锗衬底的第二区域之上，其中第一硅帽的第一厚度小于第二硅帽的第二厚度。 PMOS器件包括在第一硅帽上的第一栅极电介质。 NMOS器件包括位于第二硅帽上的第二栅极电介质。

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