公开(公告)号：US20060113664A1

公开(公告)日：2006-06-01

申请号：US11288103

申请日：2005-11-29

申请人： Masaki Shiraishi ,  Noboru Akiyama ,  Tomoaki Uno ,  Nobuyoshi Matsuura

发明人： Masaki Shiraishi ,  Noboru Akiyama ,  Tomoaki Uno ,  Nobuyoshi Matsuura

IPC分类号： H01L23/34

CPC分类号： G05F3/08 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/16 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7835 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/73221 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85375 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M7/003 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS • FET for a high-side switch and a power MOS • FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS • FET for the high-side switch is formed by a p channel vertical MOS • FET, and the power MOS • FET for the low-side switch is formed by an n channel vertical MOS • FET. Thus, a semiconductor chip formed with the power MOS • FET for the high-side switch and a semiconductor chip formed with the power MOS • FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.

摘要翻译： 本发明的目的是减少电源电路中的主电路的寄生电感。 本发明提供一种具有功率MOS的电路的非绝缘DC-DC转换器。 用于高侧开关的FET和功率MOS。 用于低侧开关的FET串联连接。 在非绝缘DC-DC转换器中，功率MOS。 用于高侧开关的FET由p沟道垂直MOS形成。 FET和功率MOS。 用于低侧开关的FET由n沟道垂直MOS形成。 FET。 因此，形成有功率MOS的半导体芯片。 用于高侧开关的FET和形成有功率MOS的半导体芯片。 用于低侧开关的FET安装在相同的芯片焊盘上并通过芯片焊盘彼此电连接。

公开(公告)号：US20060043495A1

公开(公告)日：2006-03-02

申请号：US11250392

申请日：2005-10-17

申请人： Tomoaki Uno ,  Yoshito Nakazawa

发明人： Tomoaki Uno ,  Yoshito Nakazawa

IPC分类号： H01L29/76

CPC分类号： H01L29/66727 ,  H01L23/50 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7839 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an n-channel type power MISFET, a source electrode in contact with an n+-semiconductor region (source region) and a p+-semiconductor region (back gate contact region) is constituted with an Al film and an underlying barrier film comprised of MoSi2, use of the material having higher barrier height relation to n-Si for the barrier film increasing the contact resistance to n-Si and backwardly biasing the emitter and base of a parasitic bipolar transistor making it less tending to turn-on, thereby decreasing the leak current of power MISFET.

摘要翻译： 在n沟道型功率MISFET中，与n + / - 半导体区域（源极区域）和ap + + - 半导体区域（背栅极接触区域 ）由Al膜和由MoSi 2 N构成的下面的阻挡膜构成，使用与n-Si相比具有更高的势垒高度的材料用于阻挡膜增加与n-Si的接触电阻，以及 向后偏置寄生双极晶体管的发射极和基极，使其不易于接通，从而减小功率MISFET的漏电流。

公开(公告)号：US07005834B2

公开(公告)日：2006-02-28

申请号：US10882672

申请日：2004-07-02

申请人： Takayuki Iwasaki ,  Kozo Sakamoto ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Tomoaki Uno

发明人： Takayuki Iwasaki ,  Kozo Sakamoto ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Tomoaki Uno

IPC分类号： G05F1/613 ,  G05F1/656

CPC分类号： H02M3/1588 ,  Y02B70/1466

摘要： In a power supply of a synchronous rectification type, the self-turn on phenomenon of MOSFET is suppressed without increase of the drive loss to thereby improve the power efficiency. In a synchronous rectifier circuit, a threshold value of a commutation MOSFET is made higher than that of a rectification MOSFET and particularly a threshold value of a commutation MOSFET 3 is made 0.5V or more higher than that of a rectification MOSFET 2. The threshold value of the rectification MOSFET 2 is lower than 1.5V and the threshold of the commutation MOSFET 3 is higher than 2.0V.

摘要翻译： 在同步整流型的电源中，不增加驱动损耗来抑制MOSFET的自转导通现象，从而提高功率效率。 在同步整流电路中，使换向MOSFET的阈值高于整流MOSFET的阈值，特别是使换向MOSFET 3的阈值比整流MOSFET2的阈值高0.5V以上。 整流用MOSFET2的阈值低于1.5V，换流用MOSFET3的阈值高于2.0V。

公开(公告)号：US20050007078A1

公开(公告)日：2005-01-13

申请号：US10882672

申请日：2004-07-02

申请人： Takayuki Iwasaki ,  Kozo Sakamoto ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Tomoaki Uno

发明人： Takayuki Iwasaki ,  Kozo Sakamoto ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Tomoaki Uno

IPC分类号： H02M7/21 ,  H02M3/155 ,  H02M3/158 ,  G05F1/652

CPC分类号： H02M3/1588 ,  Y02B70/1466

摘要： In a power supply of a synchronous rectification type, the self-turn on phenomenon of MOSFET is suppressed without increase of the drive loss to thereby improve the power efficiency. In a synchronous rectifier circuit, a threshold value of a commutation MOSFET is made higher than that of a rectification MOSFET and particularly a threshold value of a commutation MOSFET 3 is made 0.5V or more higher than that of a rectification MOSFET 2. The threshold value of the rectification MOSFET 2 is lower than 1.5V and the threshold of the commutation MOSFET 3 is higher than 2.0V.

摘要翻译： 在同步整流型的电源中，不增加驱动损耗来抑制MOSFET的自转导通现象，从而提高功率效率。 在同步整流电路中，使换向MOSFET的阈值高于整流MOSFET的阈值，特别是使换向MOSFET 3的阈值比整流MOSFET2的阈值高0.5V以上。阈值 的整流用MOSFET2的电压低于1.5V，换流用MOSFET3的阈值高于2.0V。

公开(公告)号：US5960259A

公开(公告)日：1999-09-28

申请号：US937131

申请日：1997-09-24

申请人： Yasuo Kitaoka ,  Kazuhisa Yamamoto ,  Makoto Kato ,  Tomoaki Uno ,  Kiminori Mizuuchi ,  Kenichi Nishiuchi

发明人： Yasuo Kitaoka ,  Kazuhisa Yamamoto ,  Makoto Kato ,  Tomoaki Uno ,  Kiminori Mizuuchi ,  Kenichi Nishiuchi

IPC分类号： G02B6/42 ,  G02F1/37 ,  H01S5/022 ,  H01S5/06 ,  H01S5/0625 ,  H01S5/0683 ,  H01S5/0687 ,  H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01S5/0687 ,  G02B6/42 ,  G02B6/4257 ,  G02B6/4272 ,  H01S5/06256 ,  G02B6/4213 ,  G02B6/4224 ,  G02B6/4271 ,  G02F1/37 ,  H01S5/0092 ,  H01S5/02252 ,  H01S5/02268 ,  H01S5/02272 ,  H01S5/0612 ,  H01S5/06837

摘要： A light generating apparatus includes: a submount; a semiconductor laser chip mounted on the submount; a substrate which is mount on the submount and includes an optical waveguide; and a substance having a predetermined thickness which is disposed between the semiconductor laser chip and the substrate. In an oscillation wavelength stabilizing apparatus for a light source, the light source is a semiconductor laser which includes: an active region for providing gain; and a distributed Bragg reflection (DBR) region for controlling an oscillation wavelength. The apparatus includes a control section which monotonously varies, in a first direction, a DBR current to be input to the DBR region while detecting the oscillation wavelength of an output light of the semiconductor laser so as to detect a DBR current value I.sub.o corresponding to a predetermined wave-length value, and then monotonously varies the DBR current in a second direction which is opposite the first direction beyond the detected value I.sub.o and then monotonously varies the DBR current in the first direction again to set the DBR current at the detected value I.sub.o, thereby fixing the oscillation wavelength of the semiconductor laser chip at the predetermined wavelength value.

摘要翻译： 一种发光装置，包括：底座; 安装在底座上的半导体激光芯片; 基板，其安装在所述基座上并且包括光波导; 以及设置在半导体激光芯片和基板之间的具有预定厚度的物质。 在用于光源的振荡波长稳定装置中，光源是半导体激光器，其包括：用于提供增益的有源区; 以及用于控制振荡波长的分布式布拉格反射（DBR）区域。 该装置包括控制部分，其在检测半导体激光器的输出光的振荡波长的同时，在第一方向上单向地变化要输入到DBR区域的DBR电流，以便检测对应于所述半导体激光器的DBR电流值Io 预定波长值，然后在与第一方向相反的第二方向上将DBR电流单调变化超过检测值Io，然后再次单向地改变第一方向上的DBR电流，以将DBR电流设定在检测值Io 从而将半导体激光器芯片的振荡波长固定在预定波长值。

公开(公告)号：US20160351702A1

公开(公告)日：2016-12-01

申请号：US14406991

申请日：2014-01-31

申请人： Hideo Numabe ,  Nobuyuki Shirai ,  Hirokazu Kato ,  Tomoaki Uno ,  Kazuyuki Umezu

发明人： Hideo Numabe ,  Nobuyuki Shirai ,  Hirokazu Kato ,  Tomoaki Uno ,  Kazuyuki Umezu

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L23/535 ,  H01L29/417 ,  H01L29/423 ,  H01L29/08

CPC分类号： H01L29/7813 ,  H01L23/535 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

摘要： A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.

摘要翻译： 控制电极GE1形成在形成在半导体衬底SUB中的沟槽TR1的下部，栅电极GE2形成在沟槽TR1内部的上部。 在控制电极GE1与沟槽TR1的侧壁和底面之间形成绝缘膜G1，在沟槽TR1的侧壁与栅电极GE2之间形成绝缘膜G2，绝缘膜G3为 形成在控制电极GE1和栅电极GE2之间。 与沟槽TR1相邻的区域包括用于源极的n +型半导体区域NR，用于沟道形成的p型半导体区域PR和用于漏极的半导体区域。 连接到控制电极GE1的布线不连接到与栅电极GE2连接的布线，并且不连接到与源的n +型半导体区域NR连接的布线。

公开(公告)号：US08482345B2

公开(公告)日：2013-07-09

申请号：US13293250

申请日：2011-11-10

申请人： Tomoaki Uno ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Toshio Nagasawa

发明人： Tomoaki Uno ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Toshio Nagasawa

IPC分类号： H01L25/00

CPC分类号： H02M1/08 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/20753

摘要： A non-insulated DC-DC converter has a power MOS•FET for a highside switch and a power MOS•FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS•FET for the highside switch and the power MOS•FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS•FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other.

摘要翻译： 非绝缘DC-DC转换器具有用于高侧开关的功率MOS.FET和用于低端开关的功率MOS.FET。 在非绝缘DC-DC转换器中，用于高侧开关的功率MOS.FET和用于低端开关的功率MOS.FET，分别控制这些元件的操作的驱动电路和与...并联连接的肖特基势垒二极管 用于低端开关的功率MOS.FET分别形成在四个不同的半导体芯片中。 这四个半导体芯片容纳在一个封装中。 半导体芯片安装在相同的芯片焊盘上。 半导体芯片被配置为彼此接近。

公开(公告)号：US08344459B2

公开(公告)日：2013-01-01

申请号：US13151952

申请日：2011-06-02

申请人： Tomoaki Uno ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Yukihiro Satou

发明人： Tomoaki Uno ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Yukihiro Satou

IPC分类号： H01L21/331

CPC分类号： H01L25/165 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73221 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H02M3/1588 ,  H03K17/6871 ,  Y02B70/1466 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are formed within one semiconductor chip, whereas the low-side switch power MOSFET is formed in another semiconductor chip. The two semiconductor chips are sealed in a single package.

摘要翻译： 本发明提高了半导体器件的电压转换效率。 在一个非隔离DC-DC转换器中，包括串联的高侧开关功率MOSFET和低侧开关功率MOSFET，高侧开关功率MOSFET和驱动电路用于驱动高边和 低侧开关功率MOSFET形成在一个半导体芯片内，而低边开关功率MOSFET则形成在另一个半导体芯片中。 两个半导体芯片被封装在单个封装中。

公开(公告)号：US08138598B2

公开(公告)日：2012-03-20

申请号：US12686595

申请日：2010-01-13

申请人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

发明人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

IPC分类号： H01L29/06

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

摘要翻译： 在具有功率MOS·FET高侧开关和功率MOS·FET低侧开关串联的电路的非绝缘DC-DC转换器中，功率MOS·FET低侧开关和肖特基 与功率MOS·FET低侧开关并联连接的二极管形成在一个半导体芯片内。 肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中央，并且在其两侧设置功率MOS·FET低侧开关的形成区域。 从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在它们之间插入形成区域SDR。

公开(公告)号：US08076767B2

公开(公告)日：2011-12-13

申请号：US12912287

申请日：2010-10-26

申请人： Tomoaki Uno ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Toshio Nagasawa

发明人： Tomoaki Uno ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Toshio Nagasawa

IPC分类号： H01L23/02

CPC分类号： H02M1/08 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/20753

摘要： A non-insulated DC-DC converter has a power MOS-FET for a highside switch and a power MOS-FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS-FET for the highside switch and the power MOS-FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS-FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other.

摘要翻译： 非绝缘DC-DC转换器具有用于高侧开关的功率MOS-FET和用于低端开关的功率MOS-FET。 在非绝缘DC-DC转换器中，用于高侧开关的功率MOS-FET和用于低端开关的功率MOS-FET，分别控制这些元件的操作的驱动电路和并联连接的肖特基势垒二极管 用于低端开关的功率MOS-FET分别形成在四个不同的半导体芯片中。 这四个半导体芯片容纳在一个封装中。 半导体芯片安装在相同的芯片焊盘上。 半导体芯片被配置为彼此接近。