公开(公告)号：US20240312890A1

公开(公告)日：2024-09-19

申请号：US18443166

申请日：2024-02-15

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  See Hiong Leow ,  Ling Pan ,  Seng Kim Ye ,  Chin Hui Chong

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2924/181 ,  H01L2924/19011

Abstract: At least one embodiment of a semiconductor device assembly include a cross-stack substrate can comprise an assembly substrate including an upper surface, a first and second die stack at the upper surface, and a cross-stack substrate spaced from the upper surface. The first and second die stacks can each include multiple semiconductor dies in electric communication with the assembly substrate, and the cross-stack substrate can be coupled to and extending between a first and a second semiconductor die of the first and second die stacks, respectively. A passive semiconductor component can be carried by the cross-stack substrate, and can be in electric communication with the assembly substrate. Further, the passive semiconductor component can be in electric communication with the first semiconductor die of the first die stack exclusively via the assembly substrate.

公开(公告)号：US11929351B2

公开(公告)日：2024-03-12

申请号：US17682948

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Seng Kim Ye ,  Hong Wan Ng ,  Hem P. Takiar

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/48228 ,  H01L2224/48229 ,  H01L2224/85045 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.

公开(公告)号：US20240079306A1

公开(公告)日：2024-03-07

申请号：US17930304

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Wen Wei Lum ,  Hong Wan Ng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/1433 ,  H01L2924/1438 ,  H01L2924/35121

Abstract: A microelectronic device package includes a microelectronic device, a masking material defined (MMD) contact, and a non-masking material defined (NMMD) contact. The microelectronic device is supported on, and electrically connected to, one of a package substrate and a redistribution layer. The MMD contact is located in a first region of the one of the package substrate and the redistribution layer and facilitates a first electrical connection between the microelectronic device and the one of the package substrate and the redistribution layer. The NMMD contact is located in a second, different region of the one of the package substrate and the redistribution layer and facilitates a second electrical connection between the microelectronic device and the one of the package substrate and the redistribution layer. Related methods and systems are also disclosed.

公开(公告)号：US20240072022A1

公开(公告)日：2024-02-29

申请号：US17899592

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Chin Hui Chong

IPC: H01L25/16 ,  H01G2/06 ,  H01G13/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/16 ,  H01G2/06 ,  H01G13/00 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/19105

Abstract: Semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having an inner surface, a die stack carried by the inner surface, and a stacked capacitor device carried by the inner surface adjacent to the die stack. The die stack can include one or more semiconductor dies, each of which can be electrically coupled to the inner surface by one or more bond wires and/or solder structures. The stacked capacitor device can include a first capacitor having a lower surface attached to the inner surface of the package substrate, a interposer having a first side attached to an upper surface of the first capacitor, and a second capacitor attached to a second side of the interposer opposite the first side.

公开(公告)号：US20240071990A1

公开(公告)日：2024-02-29

申请号：US17896030

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Hong Wan Ng ,  Ling Pan ,  See Hiong Leow

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/1318 ,  H01L2224/13181 ,  H01L2224/13183 ,  H01L2224/13184 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81469 ,  H01L2224/81473 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/8148 ,  H01L2224/81481 ,  H01L2224/81483 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/3841

Abstract: A semiconductor device assembly including a semiconductor device having a plurality of pillars disposed on a backside surface of the semiconductor device; and a substrate, including: a solder mask layer disposed on a front side surface of the substrate, a plurality of extended bond pads disposed on the frontside surface of the substrate and surrounded by the solder mask layer, the plurality of extended bond pads each having a top surface higher than a top surface of the solder mask layer, and wherein the semiconductor device is directly attached to the substrate by bonding each of the plurality of pillars of the semiconductor device to the top surface of a corresponding one of the plurality of extended bond pads with a solder connection.

公开(公告)号：US20240071979A1

公开(公告)日：2024-02-29

申请号：US17898368

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Hong Wan Ng ,  Suresh K. Upadhyayula

IPC: H01L23/00

CPC classification number: H01L24/48 ,  H01L24/06 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/06131 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85

Abstract: An assembly comprising a substrate with a first and second bond pad at a top surface; and a semiconductor die with a lower surface coupled to the top surface, an upper surface with a third and fourth bond pad thereat, and a side surface perpendicular to the upper and lower surfaces. The first bond pad can be a first distance, the second bond pad can be a second distance, the third bond pad can be a third distance, and the fourth bond pad can be a fourth distance, respectively, from the side surface. The first and third distances summed can be the same as the second and fourth distances summed. A first wire can extend between the first and third bond pads, and a second wire can extend between the second and fourth bond pads.

公开(公告)号：US20240071869A1

公开(公告)日：2024-02-29

申请号：US17894102

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Ling Pan ,  See Hiong Leow

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/481 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/5283

Abstract: A semiconductor device assembly including a substrate; a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint, wherein the first and second via lands are disposed entirely within a circular region having the first radius of curvature.

公开(公告)号：US20240038704A1

公开(公告)日：2024-02-01

申请号：US17874206

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Faxing Che ,  Hong Wan Ng ,  Yeow Chon Ong

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/16 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/81815 ,  H01L2224/81203 ,  H01L2924/37001 ,  H01L2924/3512 ,  H01L2224/16148 ,  H01L2224/16221 ,  H01L2224/11462 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/13147 ,  H01L2224/13541 ,  H01L2224/1355 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/13582

Abstract: In some embodiments, a semiconductor device assembly can include a first semiconductor die, a second semiconductor die, and an interconnection structure therebetween. The interconnection structure can directly electrically couple the first and the second semiconductor dies. The interconnection structure can include an inner metallic pillar, an outer metallic shell, a continuous metallic bridging layer, and a dielectric liner. The outer metallic shell can surround and be spaced from the inner metallic pillar, the continuous metallic bridging layer can be over and connected with the inner metallic pillar and the outer metallic shell, and the dielectric liner can be between the inner metallic pillar and the outer metallic shell. In some embodiments, the second semiconductor die can be excluded and the interconnection structure can solely be coupled to the first semiconductor die.

公开(公告)号：US11855065B2

公开(公告)日：2023-12-26

申请号：US17409439

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Seng Kim Ye

IPC: H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L24/33 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/1033 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15174 ,  H01L2924/15182 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/92247 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05599

Abstract: Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.

公开(公告)号：US20230282559A1

公开(公告)日：2023-09-07

申请号：US17686225

申请日：2022-03-03

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Chin Hui Chong ,  Kelvin Tan Aik Boo ,  Seng Kim Ye

IPC: H01L23/498 ,  H01L23/552 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/552 ,  H01L23/49816 ,  H01L21/4846 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/48 ,  H01L24/80 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/08225 ,  H01L2224/80001 ,  H01L2224/48225 ,  H01L2224/48145 ,  H01L2224/49112 ,  H01L2225/06562 ,  H01L2225/06506 ,  H01L2225/0651

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate having an upper surface on which is disposed a first device contact, a keep-out region extending from a first side surface of the substrate to a second side surface of the substrate opposite the first, and at least one trace coupled to the first device contact and extending across the keep out region towards a third side surface of the substrate. The assembly further includes at least one semiconductor device disposed over the upper surface of the substrate and coupled to the first device contact. The keep-out region of the substrate is free from conductive structures other than the at least one trace.