公开(公告)号：US20150144960A1

公开(公告)日：2015-05-28

申请号：US14091622

申请日：2013-11-27

申请人： General Electric Company

发明人： Richard Joseph Saia ,  Stephen Daley Arthur ,  Zachary Matthew Stum ,  Roger Raymond Kovalec ,  Gregory Keith Dudoff

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/16

CPC分类号： H01L29/4933 ,  H01L21/0273 ,  H01L21/049 ,  H01L21/32139 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/7802

摘要： The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

摘要翻译： 本文公开的主题涉及诸如碳化硅（SiC）功率器件（例如，MOSFET，IGBT等）的金属氧化物半导体（MOS）器件。在一个实施例中，半导体器件包括设置在 半导体层顶部。 半导体器件还包括具有锥形侧壁的栅电极。 此外，栅极包括设置在栅极氧化物层的顶部上的多晶硅层和设置在多晶硅层顶部的金属硅化物层。

公开(公告)号：US09041095B2

公开(公告)日：2015-05-26

申请号：US14161068

申请日：2014-01-22

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66666

摘要： A method of manufacturing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer, a first insulating film around the fin-shaped semiconductor layer, and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A second step forms a gate insulating film around the pillar-shaped semiconductor layer, a gate electrode around the gate insulating film, and a gate line. A third step forms a first first-conductivity-type diffusion layer in an upper portion of the pillar-shaped semiconductor layer and a second first-conductivity-type diffusion layer in a lower portion of the pillar-shaped semiconductor layer and an upper portion of the fin-shaped semiconductor layer. A fourth step includes depositing, planarizing, and etching-back a first interlayer insulating film to expose an upper portion of the pillar-shaped semiconductor layer, depositing a first metal, and etching the metal to form a first sidewall around the upper portion of the pillar-shaped semiconductor layer.

摘要翻译： 一种制造半导体器件的方法包括：形成鳍状半导体层的第一步骤，鳍状半导体层周围的第一绝缘膜和鳍状半导体层上的柱状半导体层。 第二级在柱状半导体层周围形成栅极绝缘膜，栅极绝缘膜周围的栅电极和栅极线。 第三步骤在柱状半导体层的上部形成第一第一导电型扩散层，在柱状半导体层的下部形成第二第一导电型扩散层， 鳍状半导体层。 第四步包括沉积，平坦化和蚀刻回第一层间绝缘膜以暴露柱状半导体层的上部，沉积第一金属，并蚀刻金属以形成围绕第一金属的上部的第一侧壁 柱状半导体层。

公开(公告)号：US09040367B2

公开(公告)日：2015-05-26

申请号：US13590561

申请日：2012-08-21

申请人： Da-Wei Lai

发明人： Da-Wei Lai

IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L27/02 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L27/027 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/41775 ,  H01L29/4933 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7816

摘要： An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region.

摘要翻译： 公开了一种具有增加的保持电压的改进的nLDMOS ESD保护装置。 实施例包括：在基板中提供DVNW区域; 在DVNW区域提供HVPW区域; 在HVPW区域提供批量和源区域; 在DVNW区域中提供与HVPW区域分离的漏极区域; 以及在HVPW区域和DVNW区域的一部分上提供多晶硅栅极。

公开(公告)号：US20150129974A1

公开(公告)日：2015-05-14

申请号：US14216538

申请日：2014-03-17

申请人： SK HYNIX INC

发明人： Yun-Hyuck JI

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/092

CPC分类号： H01L29/7845 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/66515 ,  H01L29/66575 ,  H01L29/78

摘要： A semiconductor device includes a first channel, a second channel, a first strained gate electrode including a first lattice-mismatched layer for applying a first stress to the first channel, and a second strained gate electrode including a second lattice-mismatched layer for applying a second stress to the second channel.

摘要翻译： 半导体器件包括第一沟道，第二沟道，包括用于向第一沟道施加第一应力的第一晶格失配层的第一应变栅电极和包括第二晶格失配层的第二应变栅电极， 第二个压力是第二个通道。

公开(公告)号：US08994101B2

公开(公告)日：2015-03-31

申请号：US13865941

申请日：2013-04-18

申请人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Jongoh Kim ,  John Chen

发明人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

IPC分类号： H01L29/772 ,  H01L29/78 ,  H01L27/088 ,  H01L21/283 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/732 ,  H01L29/423 ,  H01L21/265 ,  H01L29/45 ,  H01L29/49 ,  H01L29/10

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L21/283 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

摘要翻译： 一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。 沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。 使用第二掩模形成由中间介电区分隔的第一和第二导电区域。 使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。 使用第四掩模形成与栅极金属区域的接触。 半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

公开(公告)号：US08987107B2

公开(公告)日：2015-03-24

申请号：US13770453

申请日：2013-02-19

申请人： Fairchild Semiconductor Corporation

发明人： Daniel Hahn ,  Steven Leibiger ,  Sunglyong Kim ,  Christopher Nassar ,  James Hall

IPC分类号： H01L21/20 ,  H01L49/02 ,  H01L29/66 ,  H01L27/06 ,  H01L29/94 ,  H01L29/732

CPC分类号： H01L28/75 ,  H01L27/0629 ,  H01L27/0635 ,  H01L28/20 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66181 ,  H01L29/66272 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7322 ,  H01L29/7835 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one general aspect, a semiconductor processing method can include forming an N-type silicon region disposed within a P-type silicon substrate. The method can also include forming a field oxide (FOX) layer in the P-type silicon substrate where the FOX layer includes an opening exposing at least a portion of the N-type silicon region. The method can further include forming a reduced surface field (RESURF) oxide (ROX) layer having a first portion disposed on the exposed N-type silicon region and a second portion disposed on the FOX layer where the ROX layer includes a first dielectric layer in contact with the exposed N-type silicon region and a second dielectric layer disposed on the first dielectric layer. The method can further include forming a doped polysilicon layer having a first portion disposed on the first portion of the ROX layer and a second portion disposed on the second portion of the ROX layer.

摘要翻译： 在一般的方面，半导体处理方法可以包括形成设置在P型硅衬底内的N型硅区域。 该方法还可以包括在P型硅衬底中形成场氧化物（FOX）层，其中FOX层包括露出N型硅区域的至少一部分的开口。 该方法还可以包括形成具有设置在暴露的N型硅区域上的第一部分的还原表面场（RESURF）氧化物（ROX）层和设置在FOX层上的第二部分，其中ROX层包括第一介电层 与暴露的N型硅区域接触并且设置在第一介电层上的第二介电层。 该方法还可以包括形成掺杂多晶硅层，其具有设置在ROX层的第一部分上的第一部分和设置在ROX层的第二部分上的第二部分。

公开(公告)号：US20150069507A1

公开(公告)日：2015-03-12

申请号：US14024872

申请日：2013-09-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chih-Chang CHENG ,  Fu-Yu CHU ,  Ruey-Hsin LIU

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7835 ,  H01L21/28052 ,  H01L21/28105 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/66659 ,  H01L29/7833

摘要： A novel MOS transistor, which includes a source region, a drain region, a channel region, an isolation region, a drift region, a gate dielectric layer, a gate electrode and a field plate, is provided. The gate electrode has a first portion and a second portion. The first portion of a first conductivity type is located over the channel region and has a width equal to or greater than a distance of the gate electrode overlapped with the channel region. The second portion is un-doped and located over the isolation region. Accordingly, the MOS transistor allows higher process freedom saves production cost, as well as improves reliability.

摘要翻译： 提供了一种新颖的MOS晶体管，其包括源极区，漏极区，沟道区，隔离区，漂移区，栅极介电层，栅电极和场板。 栅电极具有第一部分和第二部分。 第一导电类型的第一部分位于沟道区上方，并且具有等于或大于与沟道区重叠的栅电极的距离的宽度。 第二部分是未掺杂的并且位于隔离区上方。 因此，MOS晶体管允许更高的工艺自由度节省生产成本，并提高可靠性。

公开(公告)号：US08969202B2

公开(公告)日：2015-03-03

申请号：US14174931

申请日：2014-02-07

申请人： Macronix International Co., Ltd.

发明人： Yen-Hao Shih ,  Ying-Tso Chen ,  Shih-Chang Tsai ,  Chun-Fu Chen

IPC分类号： H01L21/44 ,  H01L21/8234 ,  H01L21/302 ,  H01L21/461 ,  H01L21/283 ,  H01L27/105 ,  H01L21/28 ,  H01L29/49 ,  H01L27/118

CPC分类号： H01L21/283 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/823443 ,  H01L27/1052 ,  H01L29/4933

摘要： A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.

摘要翻译： 以下公开了金属硅化物的制造方法。 提供具有第一区域和第二区域的衬底。 在衬底上形成硅层。 进行平面化处理以使硅层具有平坦表面。 去除硅层的一部分以在第一区域上形成多个第一栅极，并在第二区域上形成多个第二栅极。 第一栅极的高度大于第二栅极的高度，并且第一栅极和第二栅极的顶表面具有相同的高度水平。 覆盖第一栅极和第二栅极的电介质层形成并露出第一栅极和第二栅极的顶表面。 金属硅化物形成在第一栅极和第二栅极的顶表面上。

公开(公告)号：US08951916B2

公开(公告)日：2015-02-10

申请号：US14033952

申请日：2013-09-23

申请人： Tela Innovations, Inc.

发明人： Michael C. Smayling

IPC分类号： H01L21/467 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/49

CPC分类号： H01L27/092 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823807 ,  H01L21/823828 ,  H01L23/481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

摘要： A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.

摘要翻译： 多个第一硬掩模部分形成在电介质层上以垂直地遮蔽多个下面的栅极结构中的相应一个。 在每个第一硬掩模部分的每个侧表面附近形成多个第二硬掩模长丝。 将每个第二硬掩模灯丝的宽度设置为限定有源区域接触 - 栅极结构间隔。 在给定的一对相邻的第二硬掩模长丝的相对的暴露的侧表面之间蚀刻第一通道并且通过半导体晶片的深度到有源区域。 通过给定的第一硬掩模部分并通过半导体晶片的深度蚀刻第二通道到下面的栅极结构的顶表面。 导电材料沉积在第一和第二通道内，以分别形成有源区接触和栅极接触。

公开(公告)号：US08937350B2

公开(公告)日：2015-01-20

申请号：US14170430

申请日：2014-01-31

申请人： Renesas Electronics Corporation

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L27/108 ,  H01L29/78 ,  H01L27/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/872 ,  H01L21/265 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.