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343 条记录 (耗时 0.018 秒)

    Microcooling device
    61.
    发明授权
    Microcooling device 失效
    微冷装置

    公开(公告)号：US06812563B2

    公开(公告)日：2004-11-02

    申请号：US10198133

    申请日：2002-07-19

    申请人： Jeung-sang Go ,  Tae-gyun Kim ,  Kyung-il Cho

    发明人： Jeung-sang Go ,  Tae-gyun Kim ,  Kyung-il Cho

    IPC分类号： H01L2334

    CPC分类号： H01L23/473 ,  H01L2924/0002 ,  Y10S257/93 ,  H01L2924/00

    摘要： A microcooling device is provided. The microcooling device includes a substrate, a microchannel array, and a condenser. A predetermined region of a lower surface of the substrate contacts a heat source. The microchannel array is placed on the substrate so that a coolant concentrating portion is opposite to the predetermined region of the lower surface. The condenser fixes the microchannel array, condenses vapor generated in a process of cooling the heat source, and allows the condensed vapor to flow into the microchannel array.

    摘要翻译： 提供了一个微型冷却装置。 微冷装置包括基板，微通道阵列和冷凝器。 基板的下表面的预定区域接触热源。 微通道阵列放置在基板上，使得冷却剂集中部分与下表面的预定区域相对。 冷凝器固定微通道阵列，冷凝在冷却热源的过程中产生的蒸气，并使冷凝的蒸汽流入微通道阵列。

    Structure for contact formation using a silicon-germanium alloy
    62.
    发明授权
    Structure for contact formation using a silicon-germanium alloy 失效
    使用硅 - 锗合金的接触形成结构

    公开(公告)号：US06806572B2

    公开(公告)日：2004-10-19

    申请号：US10277688

    申请日：2002-10-22

    申请人： Randhir P. S. Thakur

    发明人： Randhir P. S. Thakur

    IPC分类号： H01L2334

    CPC分类号： H01L21/76831 ,  H01L21/28525 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76879 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

    摘要： A new method and structure for an improved contact using doped silicon is provided. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device and subsequent metallization layers. The improvements are obtained through the use of a silicon-germanium (Si—Ge) alloy. The alloy can be formed from depositing germanium onto the substrate and subsequently annealing the contact or by selectively depositing the preformed alloy into a contact opening. The above advantages are incorporated with relatively few process steps.

    摘要翻译： 提供了一种使用掺杂硅改善接触的新方法和结构。 这些结构被集成到几个较高级别的实施例中。 改进的接触具有低接触电阻率。 因此，在IGFET器件和随后的金属化层之间提供改进的结。 通过使用硅 - 锗（Si-Ge）合金获得改进。 该合金可以通过将锗沉积到基底上并随后对接触进行退火或通过选择性地将预成型合金沉积到接触开口中而形成。 上述优点结合相对较少的工艺步骤。

    Multi-frequency power delivery system
    63.
    发明授权
    Multi-frequency power delivery system 有权
    多频送电系统

    公开(公告)号：US06806569B2

    公开(公告)日：2004-10-19

    申请号：US09964811

    申请日：2001-09-28

    申请人： James E. Breisch ,  Mark A. Beiley

    发明人： James E. Breisch ,  Mark A. Beiley

    IPC分类号： H01L2334

    CPC分类号： H01L23/48 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

    摘要： A mechanism is provided for delivering power to an on-die component (such as a buffer circuit). This may include a package unit having a low frequency delivery path and a high frequency delivery path and a die having the on-die component and a capacitive device each coupled in parallel between a first node and a second node. The die may further include a low frequency reception path and a high frequency reception path. The low frequency reception path may couple to the low frequency delivery path on the package unit and to the first node. The high frequency reception path may couple to the high frequency delivery path on the package unit and to the first node. The high frequency reception path may include a damping resistor.

    摘要翻译： 提供了一种用于将功率传递到片上组件（例如缓冲电路）的机制。 这可以包括具有低频传送路径和高频传送路径的封装单元，以及具有片上部件的管芯和在第一节点和第二节点之间并联耦合的电容器件。 芯片还可以包括低频接收路径和高频接收路径。 低频接收路径可以耦合到封装单元上的低频传送路径和第一节点。 高频接收路径可以耦合到封装单元上的高频传输路径和第一节点。 高频接收路径可以包括阻尼电阻器。

    Package structure with increased capacitance and method
    67.
    发明授权
    Package structure with increased capacitance and method 有权
    具有增加电容和方法的封装结构

    公开(公告)号：US06787902B1

    公开(公告)日：2004-09-07

    申请号：US10401379

    申请日：2003-03-27

    申请人： Mahadevan Survakumar

    发明人： Mahadevan Survakumar

    IPC分类号： H01L2334

    CPC分类号： H01L23/50 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/00014 ,  H05K1/162 ,  H05K3/0032 ,  H05K3/4644 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09672 ,  H01L2224/0401

    摘要： A package with increased capacitance comprises a core and a plurality of buildup layers. The core has an inner dielectric portion and the core outer conductive layer. The buildup layers are disposed over the core and have offset ablated regions reducing the thickness of the buildup layers in the ablated regions. Conductive material is plated on the buildup layers including within the ablated regions. The reduced thickness and increased plate area due to the ablated regions increases the capacitance between adjacent buildup layers. Processors and processing systems may take advantage of the increased capacitance in the package to draw more current and operate at higher data rates.

    摘要翻译： 具有增加电容的封装包括芯和多个堆积层。 芯具有内绝缘部分和芯外导电层。 堆积层设置在芯上并且具有偏移的消融区域以减小烧蚀区域中积聚层的厚度。 导电材料镀在包括烧蚀区域内的积层上。 由于烧蚀区域减小的厚度和增加的板面积增加了相邻堆积层之间的电容。 处理器和处理系统可以利用增加的封装中的电容来绘制更多的电流并以更高的数据速率工作。