公开(公告)号：US20140232477A1

公开(公告)日：2014-08-21

申请号：US13803308

申请日：2013-03-14

Applicant: Jae-Jin Park ,  Hee-Seok Lee ,  Ji-Hwan Hyun ,  Kang-Yeop Choo

Inventor： Jae-Jin Park ,  Hee-Seok Lee ,  Ji-Hwan Hyun ,  Kang-Yeop Choo

IPC: H03H9/10

CPC classification number: H03H9/0542 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15331 ,  H03H9/0547 ,  H03H9/1014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/45099

Abstract: A semiconductor package includes a package substrate; an integrated circuit chip formed on one surface of the package substrate; and a sealed quartz oscillator formed on at least one of an inside, one surface, and the other surface of the package substrate, wherein the sealed quartz oscillator includes a substrate, a quartz blank formed on one surface of the substrate, and a sealing cap covering at least one surface of the quartz blank and including metal.

Abstract translation: 半导体封装包括封装衬底; 形成在所述封装基板的一个表面上的集成电路芯片; 以及密封石英振荡器，其形成在所述封装基板的内表面和所述另一表面中的至少一个表面上，其中所述密封石英振荡器包括基板，形成在所述基板的一个表面上的石英片，以及密封盖 覆盖石英坯料的至少一个表面并且包括金属。

公开(公告)号：US08587096B2

公开(公告)日：2013-11-19

申请号：US13172174

申请日：2011-06-29

Applicant: Yong-hoon Kim ,  Hee-seok Lee ,  Jin-Ha Jeong ,  Ji-hyun Lee

Inventor： Yong-hoon Kim ,  Hee-seok Lee ,  Jin-Ha Jeong ,  Ji-hyun Lee

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0233 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device may include a first semiconductor chip including a semiconductor substrate, a first through via that penetrates the semiconductor substrate, a second semiconductor chip stacked on one plane of the first semiconductor chip, and a shielding layer covering at least one portion of the first and/or second semiconductor chip and electrically connected to the first through via.

Abstract translation: 示例实施例涉及半导体器件。 半导体器件可以包括第一半导体芯片，其包括半导体衬底，穿透半导体衬底的第一通孔，堆叠在第一半导体芯片的一个平面上的第二半导体芯片，以及覆盖第一半导体衬底的至少一部分的屏蔽层 和/或第二半导体芯片，并且电连接到第一通孔。

公开(公告)号：US20120064827A1

公开(公告)日：2012-03-15

申请号：US13229193

申请日：2011-09-09

Applicant: Yong-Hoon KIM ,  Jong-Joo Lee ,  Sang-Youb Lee ,  Young-Don Choi ,  Hee-Seok Lee

Inventor： Yong-Hoon KIM ,  Jong-Joo Lee ,  Sang-Youb Lee ,  Young-Don Choi ,  Hee-Seok Lee

IPC: H04B5/00

CPC classification number: H01L23/645 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H04B5/0012 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0075 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Abstract translation: 公开了一种包括通孔的半导体器件。 半导体器件可以包括第一半导体芯片，其包括形成在第一表面上的收发器电路，形成在与第一表面相对的第二表面上的第一耦合导体图案，以及连接收发器电路和第一耦合导电 模式。 可以存在位于第二半导体芯片上的收发器，并且包括面向与第一耦合导电图案无线通信的第一耦合导电图案的第二耦合导电图案。

公开(公告)号：US20110241168A1

公开(公告)日：2011-10-06

申请号：US13045103

申请日：2011-03-10

Applicant: YONG-HOON KIM ,  Byeong-Yeon Cho ,  Hee-Seok Lee

Inventor： YONG-HOON KIM ,  Byeong-Yeon Cho ,  Hee-Seok Lee

IPC: H01L23/58

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0652 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A package on package structure includes a lower package and an upper package. The lower package includes a first semiconductor chip disposed in a chip region of an upper surface of a first substrate. The upper package includes a second semiconductor chip disposed on an upper surface of a second substrate, and a decoupling capacitor disposed in an outer region of a lower surface of the second substrate. The lower surface of the second substrate opposes the upper surface of the second substrate and faces the upper surface of the first substrate. The plane area of the second substrate is larger than the plane area of the first substrate. The outer region of the lower surface of the second substrate extends beyond a periphery of the first substrate.

Abstract translation: 包装结构上的包装包括下包装和上包装。 下封装包括设置在第一基板的上表面的芯片区域中的第一半导体芯片。 上部封装包括设置在第二基板的上表面上的第二半导体芯片和设置在第二基板的下表面的外部区域中的去耦电容器。 第二基板的下表面与第二基板的上表面相对并且面向第一基板的上表面。 第二基板的平面面积大于第一基板的平面面积。 第二基板的下表面的外部区域延伸超出第一基板的周边。

公开(公告)号：US07760044B2

公开(公告)日：2010-07-20

申请号：US11761416

申请日：2007-06-12

Applicant: Eun-seok Song ,  Hee-seok Lee ,  So-young Lim

Inventor： Eun-seok Song ,  Hee-seok Lee ,  So-young Lim

IPC: H04B3/28

CPC classification number: H01Q15/006

Abstract: A substrate for a semiconductor package comprises a dielectric substrate, a circuit pattern, and an electromagnetic band gap (EBG) pattern. The circuit pattern is formed on a first surface of the dielectric substrate and is connected to ground via a ground connection. The electromagnetic band gap (EBG) pattern comprises a plurality of zigzag unit structures formed on a second surface of the dielectric substrate, wherein the second surface is formed on an opposite side of the dielectric substrate from the first surface; the zigzag unit structures are electrically connected to each other; and at least one of the zigzag unit structures is electrically connected to the ground connection.

Abstract translation: 用于半导体封装的衬底包括电介质衬底，电路图案和电磁带隙（EBG）图案。 电路图案形成在电介质基板的第一表面上，并通过接地连接接地。 电磁带隙（EBG）图案包括形成在电介质基板的第二表面上的多个之字形单元结构，其中第二表面形成在电介质基板的与第一表面相反的一侧上; 之字形单元结构彼此电连接; 并且所述之字形单元结构中的至少一个电连接到所述接地连接。

公开(公告)号：US07705433B2

公开(公告)日：2010-04-27

申请号：US11870533

申请日：2007-10-11

Applicant: Hee-seok Lee ,  Yun-seok Choi ,  Eun-seok Song

Inventor： Hee-seok Lee ,  Yun-seok Choi ,  Eun-seok Song

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor package includes a chip including a conductive pattern thereon, a conductive network attached on a surface of the chip to absorb static electricity, at least one conductive rod attached to the conductive network, wherein the at least one conductive rod is formed substantially perpendicularly to the conductive network, and a grounding portion discharging the static electricity absorbed from the conductive network.

Abstract translation: 半导体封装包括其上包括导电图案的芯片，附接在芯片的表面上以吸收静电的导电网络，附接到导电网络的至少一个导电棒，其中至少一个导电棒基本上垂直于 导电网络，以及放电从导电网吸收的静电的接地部分。

公开(公告)号：US20100006869A1

公开(公告)日：2010-01-14

申请号：US12502324

申请日：2009-07-14

Applicant: Yun-Seok CHOI ,  Hee-Seok LEE

Inventor： Yun-Seok CHOI ,  Hee-Seok LEE

IPC: H01L33/00 ,  H01L23/52 ,  H05K1/02 ,  H01L23/48

CPC classification number: H01L23/4985 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/60 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip can include a semiconductor substrate, an input portion and an output portion. A circuit element can be formed in the semiconductor substrate. The input portion can be formed on the semiconductor substrate. The input portion can include a first input pad to receive an input signal from the outside and a second input pad spaced apart from the first input pad, the second input pad being electrically connected to the first input pad through an external connection line such that the second input pad inputs the input signal to the circuit element. The output portion can be formed on the semiconductor substrate. The output pad can include an output pad to output an output signal from the circuit element.

Abstract translation: 半导体芯片可以包括半导体衬底，输入部分和输出部分。 电路元件可以形成在半导体衬底中。 输入部分可以形成在半导体衬底上。 输入部分可以包括用于从外部接收输入信号的第一输入焊盘和与第一输入焊盘间隔开的第二输入焊盘，第二输入焊盘通过外部连接线电连接到第一输入焊盘，使得 第二输入焊盘将输入信号输入到电路元件。 输出部分可以形成在半导体衬底上。 输出焊盘可以包括输出焊盘以输出来自电路元件的输出信号。

公开(公告)号：US20080087988A1

公开(公告)日：2008-04-17

申请号：US11870533

申请日：2007-10-11

Applicant: Hee-seok Lee ,  Yun-seok Choi ,  Eun-seok Song

Inventor： Hee-seok Lee ,  Yun-seok Choi ,  Eun-seok Song

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor package includes a chip including a conductive pattern thereon, a conductive network attached on a surface of the chip to absorb static electricity, at least one conductive rod attached to the conductive network, wherein the at least one conductive rod is formed substantially perpendicularly to the conductive network, and a grounding portion discharging the static electricity absorbed from the conductive network.

Abstract translation: 半导体封装包括其上包括导电图案的芯片，附接在芯片的表面上以吸收静电的导电网络，附接到导电网络的至少一个导电棒，其中至少一个导电棒基本上垂直于 导电网络，以及放电从导电网吸收的静电的接地部分。

公开(公告)号：US20060097404A1

公开(公告)日：2006-05-11

申请号：US11259707

申请日：2005-10-25

Applicant: Byeong-Yeon Cho ,  Hee-Seok Lee ,  Kyung-Lae Jang

Inventor： Byeong-Yeon Cho ,  Hee-Seok Lee ,  Kyung-Lae Jang

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/85 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L2224/85913 ,  H01L2224/8592 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/06 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: The present invention relates to a semiconductor package having a conductive molding compound to prevent static charge accumulation. By using a conductive molding compound heat conductivity is also increased and heat generated by the semiconductor chip is more effectively dissipated externally. Additionally, the conductive compound blocks electromagnetic waves making possible an optimal semiconductor package satisfying the electromagnetic compatibility (EMC) and increasing the reliability of the semiconductor chip especially when processing high-speed signals.

Abstract translation: 本发明涉及一种具有导电性成型化合物以防止静电积聚的半导体封装。 通过使用导电模塑料，导热性也增加，并且由半导体芯片产生的热量更有效地从外部消散。 此外，导电化合物阻止电磁波，使得能够实现满足电磁兼容性（EMC）的最佳半导体封装，并且特别是在处理高速信号时增加半导体芯片的可靠性。

公开(公告)号：US20050242426A1

公开(公告)日：2005-11-03

申请号：US11110443

申请日：2005-04-19

Applicant: Heung-Kyu Kwon ,  Kyung-Lae Jang ,  Hee-Seok Lee

Inventor： Heung-Kyu Kwon ,  Kyung-Lae Jang ,  Hee-Seok Lee

IPC: H01L25/18 ,  H01L21/44 ,  H01L21/56 ,  H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L23/495 ,  H01L23/50 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L23/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48482 ,  H01L2224/48499 ,  H01L2224/48599 ,  H01L2224/48799 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/85051 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In one embodiment, a semiconductor package comprises a base frame and a lower semiconductor chip electrically coupled to the base frame. The lower semiconductor chip has a first bond pad formed on a top surface thereof. The package further includes an upper semiconductor chip overlying the lower semiconductor chip. The upper semiconductor chip has a third bond pad formed on a bottom surface thereof. The package comprises a first conductive bump and a second conductive bump jointly coupling the first bond pad to the third bond pad.

Abstract translation: 在一个实施例中，半导体封装包括电连接到基架的底架和下半导体芯片。 下半导体芯片具有形成在其顶表面上的第一接合焊盘。 封装还包括覆盖下半导体芯片的上半导体芯片。 上半导体芯片具有形成在其底表面上的第三接合焊盘。 封装包括第一导电凸块和将第一接合焊盘联接到第三接合焊盘的第二导电凸块。