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103 条记录 (耗时 0.035 秒)

    Flexible structures for interconnect reliability test
    72.
    发明授权
    Flexible structures for interconnect reliability test 有权
    用于互连可靠性测试的柔性结构

    公开(公告)号：US07776627B2

    公开(公告)日：2010-08-17

    申请号：US11971072

    申请日：2008-01-08

    申请人： Shin-Puu Jeng ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N. F. Wu

    发明人： Shin-Puu Jeng ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N. F. Wu

    IPC分类号： H01L21/66

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of the first plurality of unit blocks includes a plurality of connection block cells arranged as an array. Each of the connection block cells includes two connection blocks, and a metal line connecting the two connection blocks. The method further includes forming a plurality of unit block boundary lines separating the first plurality of unit blocks from each other; and forming a first plurality of metal lines connecting a portion of the first plurality of unit blocks.

    摘要翻译： 一种用于形成集成电路结构的方法包括形成测试晶片。 形成测试晶片的步骤包括提供第一半导体衬底; 以及在所述第一半导体衬底上形成第一多个单元块。 第一多个单元块中的每一个包括被排列成阵列的多个连接块单元。 每个连接块单元包括两个连接块和连接两个连接块的金属线。 该方法还包括形成将第一多个单元块彼此分离的多个单元块边界线; 以及形成连接所述第一多个单元块的一部分的第一多个金属线。

    Scribe line layout design
    74.
    发明申请
    Scribe line layout design 有权
    划线设计

    公开(公告)号：US20080265378A1

    公开(公告)日：2008-10-30

    申请号：US11796202

    申请日：2007-04-27

    申请人： Hsin-Hui Lee ,  Mirng-Ji Lii ,  Shin-Puu Jeng ,  Shang-Yun Hou

    发明人： Hsin-Hui Lee ,  Mirng-Ji Lii ,  Shin-Puu Jeng ,  Shang-Yun Hou

    IPC分类号： H01L23/544

    CPC分类号： H01L23/544 ,  H01L23/585 ,  H01L2223/5442 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A scribe line layout design to reduce the damage caused by sawing the wafer is presented. An embodiment comprises metal plates located within the scribe lines and at least partially within the junctions of the scribe lines. Each of these metal plates has one or more slots to help relieve the pressure. Alternatively, instead of metal plates, grooves that may be filled with metal could be placed into the scribe lines. These metal plates could also be used concurrently with a seal ring for better protection during sawing.

    摘要翻译： 提出了一种划线设计，以减少锯切锯片造成的损坏。 一个实施例包括位于划线内且至少部分地位于划线内的金属板。 这些金属板中的每一个具有一个或多个槽以帮助减轻压力。 或者，代替金属板，可以将填充有金属的凹槽放置在划线中。 这些金属板也可以与密封环同时使用，以便在锯切期间更好地保护。

    Through silicon via keep out zone formation along different crystal orientations
    78.
    发明授权
    Through silicon via keep out zone formation along different crystal orientations 有权
    通过硅通过沿着不同的晶体取向保持区域形成

    公开(公告)号：US08604619B2

    公开(公告)日：2013-12-10

    申请号：US13302653

    申请日：2011-11-22

    申请人： Cheng-Chieh Hsieh ,  Hung-An Teng ,  Shang-Yun Hou ,  Shin-Puu Jeng

    发明人： Cheng-Chieh Hsieh ,  Hung-An Teng ,  Shang-Yun Hou ,  Shin-Puu Jeng

    IPC分类号： H01L23/48

    CPC分类号： H01L23/562 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.

    摘要翻译： 为硅通孔（TSV）形成保留区（KOZ）。 设备可以放置在由第一性能阈值确定的TSV的第一KOZ之外，使得由设备的TSV引起的应力冲击小于第一性能阈值，而第一KOZ仅包含应力冲击的那些点 由TSV引起的大于或等于第一个性能阈值。 用于TSV的第二KOZ可以类似地由第二性能阈值形成。 多个TSV可以沿着TSV的KOZ具有最小半径的方向被放置到TSV的中心，其可以是晶体取向[010]或[100]。 可以在多个TSV的整个KOZ的边界处形成多个TSV应力塞。