公开(公告)号：US06667546B2

公开(公告)日：2003-12-23

申请号：US10039884

申请日：2002-01-03

申请人： Chien-Ping Huang ,  Eric Ko ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Eric Ko ,  Chih-Ming Huang

IPC分类号： H01L2310

CPC分类号： H01L24/85 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8485 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： A ball grid array semiconductor package is proposed, wherein at least a chip is mounted on a substrate, and signal pads on the chip are electrically connected to signal fingers on the substrate by bonding wires. A power plate and a ground plate are each attached at two ends thereof respectively to predetermined positions on the chip and substrate, without interfering with the bonding wires. No power ring or ground ring is necessarily formed on the substrate, thereby reducing restriction on trace routability of the substrate. Further, with no provision of power wires or ground wires, short circuit of the bonding wires is less likely to occur, and thus production yield is enhanced. In addition, the power plate and ground plate provide shielding effect for protecting the chip against external electric-magnetic interference, and are partly in direct contact with the atmosphere for improving heat dissipating efficiency of the semiconductor package.

摘要翻译： 提出了一种球栅阵列半导体封装，其中至少芯片安装在基板上，并且芯片上的信号焊盘通过接合线与基板上的信号指状电连接。 功率板和接地板分别在其两端分别连接到芯片和基板上的预定位置，而不会妨碍接合线。 在基板上不必形成功率环或接地环，从而减少对基板的微量可路由性的限制。 此外，由于不设置电源线或接地线，因此不太可能发生接合线的短路，从而提高了生产率。 此外，功率板和接地板提供屏蔽效果，用于保护芯片免受外部电磁干扰，并且部分地与大气直接接触，以提高半导体封装的散热效率。

公开(公告)号：US08546183B2

公开(公告)日：2013-10-01

申请号：US12241847

申请日：2008-09-30

申请人： Chien-Ping Huang ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Chih-Ming Huang

IPC分类号： H01L21/02

CPC分类号： H01L23/3677 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3733 ,  H01L23/4334 ,  H01L23/49548 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/351 ,  Y10T29/49126 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A heat dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted on a chip carrier. A heat sink is mounted on the chip, and includes an insulating core layer, a thin metallic layer formed on each of an upper surface and a lower surface of the insulating core layer and a thermal via hole formed in the insulating core layer. A molding process is performed to encapsulate the chip and the heat sink with an encapsulant to form a package unit. A singulation process is performed to peripherally cut the package unit. A part of the encapsulant above the thin metallic layer on the upper surface of the heat sink is removed, such that the thin metallic layer on the upper surface of the heat sink is exposed, and heat generated by the chip can be dissipated through the heat sink.

摘要翻译： 提供散热半导体封装及其制造方法。 半导体芯片安装在芯片载体上。 散热器安装在芯片上，并且包括绝缘芯层，形成在绝缘芯层的上表面和下表面中的每一个上的薄金属层和形成在绝缘芯层中的热通孔。 进行成型工艺以用密封剂封装芯片和散热器以形成封装单元。 执行单个处理以周边地切割包装单元。 在散热器的上表面上的薄金属层上方的一部分密封剂被去除，使得散热器上表面上的薄金属层被暴露，并且由芯片产生的热量可以通过热量散发 水槽。

公开(公告)号：US20120241937A1

公开(公告)日：2012-09-27

申请号：US13492220

申请日：2012-06-08

申请人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

发明人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

IPC分类号： H01L23/498

CPC分类号： H01L21/02 ,  B81B7/007 ,  B81B2207/07 ,  H01L23/52 ,  H01L29/84 ,  H01L2224/02166 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

摘要： Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.

摘要翻译： 提出具有微机电（MEMS）元件的封装结构，其包括具有多个电连接焊盘和形成在其上的MEMS元件的芯片; 设置在所述芯片上用于覆盖所述MEMS元件的盖; 设置在每个电连接焊盘上的螺柱凸块; 形成在芯片上的密封剂，其中一部分柱状凸块从密封剂暴露出来; 以及金属导电层，形成在密封剂上并连接到凸块上。 本发明的特征在于直接完成晶片上的封装工艺，以便在更短的时间内制造更薄和更便宜的封装结构。 本发明还提供如上所述的用于制造封装结构的方法。

公开(公告)号：US07816187B2

公开(公告)日：2010-10-19

申请号：US12204066

申请日：2008-09-04

申请人： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L21/00

CPC分类号： H01L21/4832 ,  H01L21/4857 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

摘要翻译： 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US20090166831A1

公开(公告)日：2009-07-02

申请号：US12344988

申请日：2008-12-29

申请人： Tse-Wen Chang ,  Chang-Yueh Chan ,  Chin-Huang Chang ,  Chih-Ming Huang

发明人： Tse-Wen Chang ,  Chang-Yueh Chan ,  Chin-Huang Chang ,  Chih-Ming Huang

IPC分类号： H01L23/04 ,  H01L21/50

CPC分类号： H01L27/14618 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L27/14683 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00

摘要： This invention provides a sensor semiconductor package and a method for fabricating the same. The method includes: mounting on a substrate a sensor chip having a sensor area; electrically connecting the sensor chip and the substrate by means of bonding wires; forming on a transparent member an adhesive layer with an opening corresponding in position to the sensor area; and mounting the transparent member on the substrate via the adhesive layer while heating the substrate, such that the adhesive layer melts, to thereby encapsulate the periphery of the sensor chip and the bonding wires while exposing the sensor area from the adhesive layer. Thus, the sensor area is sealed by the transparent member cooperative with the adhesive layer, making the sensor semiconductor package thus-obtained dam-free, light, thin, and compact, and incurs low process costs. Also, the product reliability is enhanced since the bonding wires are encapsulated by the adhesive layer without severing concern.

摘要翻译： 本发明提供一种传感器半导体封装及其制造方法。 该方法包括：在基板上安装具有传感器区域的传感器芯片; 通过接合线电连接传感器芯片和基板; 在透明构件上形成具有对应于传感器区域的位置的开口的粘合剂层; 并且通过粘合剂层将透明构件安装在基板上，同时加热基板，使得粘合剂层熔化，从而在将传感器区域从粘合剂层暴露出来的同时封装传感器芯片和接合线的周边。 因此，传感器区域与透明构件密封，与粘合剂层协作，使得传感器半导体封装得到无阻尼，轻薄，紧凑，并且导致低的工艺成本。 而且，由于接合线被粘合剂层封装而不会被切断，所以产品的可靠性得到提高。

公开(公告)号：US20080303111A1

公开(公告)日：2008-12-11

申请号：US12156901

申请日：2008-06-05

申请人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Tse-Wen Chang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

发明人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Tse-Wen Chang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L31/0203 ,  H01L31/18

CPC分类号： H01L31/0203 ,  H01L23/24 ,  H01L31/18 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention discloses a sensor package and a method for fabricating the same. The sensor package includes: a substrate with an opening; a sensor chip disposed in the opening and electrically connected to the substrate; an encapsulant filling spacing between the sensor chip and the opening so as to secure the sensor chip to the substrate; and a transparent cover attached to the substrate via an adhesive layer, wherein the adhesive layer covers the sensor chip and bonding wires and is formed with an opening for exposing sensor region of the sensor chip. Securing the sensor chip in the opening of the substrate reduces the height of the sensor package, and meanwhile the process cost is reduced by eliminating the need of formation of conductive bumps on the sensor chip or the transparent cover and eliminating the need of specially designed substrate.

摘要翻译： 本发明公开了一种传感器封装及其制造方法。 传感器封装包括：具有开口的基板; 传感器芯片，其布置在所述开口中并电连接到所述基板; 传感器芯片和开口之间的密封剂填充间隔，以将传感器芯片固定到基板上; 以及通过粘合剂层附着到基板的透明盖，其中粘合剂层覆盖传感器芯片和接合线，并且形成有用于暴露传感器芯片的传感器区域的开口。 将传感器芯片固定在基板的开口中，降低传感器封装的高度，同时通过消除在传感器芯片或透明盖上形成导电凸块的需要降低工艺成本，并且不需要特别设计的基板 。

公开(公告)号：US20080265385A1

公开(公告)日：2008-10-30

申请号：US12215543

申请日：2008-06-27

申请人： Han-Lung Tsai ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

发明人： Han-Lung Tsai ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/60 ,  H01L23/495

CPC分类号： H01L24/85 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48465 ,  H01L2224/48475 ,  H01L2224/4848 ,  H01L2224/48482 ,  H01L2224/48499 ,  H01L2224/48599 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/4554

摘要： A semiconductor package using copper wires and a wire bonding method for the same are proposed. The package includes a carrier having fingers and a chip mounted on the carrier. The method includes implanting stud bumps on the fingers of the carrier and electrically connecting the chip and the carrier by copper wires with one ends of the copper wires being bonded to bond pads of the chip and the other ends of the copper wires being bonded to the stud bumps on the carrier. The implanted stud bumps on the carrier improve bondability of the copper wires to the carrier and thus prevent stitch lift. With good bonding, residues of copper wires left behind after a bonding process have even tail ends and uniform tail length to enable fabrication of solder balls of uniform size, thereby eliminating a conventional step of implanting stud bumps on the bond pads of chips and preventing ball lift from occurring.

摘要翻译： 提出了使用铜线的半导体封装及其引线接合方法。 封装包括具有指状物的载体和安装在载体上的芯片。 该方法包括在支架的指状物上注入螺柱凸块，并用铜线电连接芯片和载体，铜线的一端被接合到芯片的接合焊盘，并且铜线的另一端被接合到 支架上的螺柱凸起。 载体上植入的柱形突起提高了铜线对载体的粘结性，从而防止了针迹提升。 通过良好的接合，在接合工艺之后留下的铜线的残留物具有均匀的尾端和均匀的尾部长度，以使得能够制造均匀尺寸的焊球，从而消除了在芯片的接合焊盘上植入凸块凸起并防止球的常规步骤 提升不发生。

公开(公告)号：US20080258306A1

公开(公告)日：2008-10-23

申请号：US12105538

申请日：2008-04-18

申请人： Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao ,  Cheng-Chia Chiang

发明人： Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao ,  Cheng-Chia Chiang

IPC分类号： H01L23/538 ,  H01L21/56

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/82001 ,  H01L2224/97 ,  H01L2225/06562 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2224/82 ,  H01L2924/01028 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a chip having an active surface and an opposing non-active surface, wherein a plurality of bond pads are formed on the active surface, and first metal layers are formed on the bond pads and to edges of the non-active surface; conductive traces disposed on the non-active surface of the chip; a dielectric layer covering sides of the chip and formed with a plurality of openings therein to expose a portion of the conductive traces; and a plurality of second metal layers formed in the openings of the dielectric layer and on the first metal layers, such that the bond pads are electrically connected to the conductive traces via the first and second metal layers.

摘要翻译： 本发明提供一种半导体器件及其制造方法。 半导体器件包括具有活性表面和相对的非活性表面的芯片，其中在有源表面上形成多个接合焊盘，并且第一金属层形成在接合焊盘和非活性表面的边缘上 ; 布置在芯片的非有源表面上的导电迹线; 介电层，其覆盖所述芯片的侧面并​​在其中形成有多个开口以暴露所述导电迹线的一部分; 以及多个第二金属层，形成在电介质层的开口中和第一金属层上，使得接合焊盘经由第一和第二金属层电连接到导电迹线。

公开(公告)号：US20080251937A1

公开(公告)日：2008-10-16

申请号：US12082724

申请日：2008-04-11

申请人： Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

发明人： Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/00014

摘要： A stackable semiconductor device and a manufacturing method thereof are disclosed. The method includes providing a wafer comprised of a plurality of chips, wherein a plurality of solder pads are formed on the active surface of each chip, and a plurality of grooves are formed between the solder pads of any two adjacent ones of the chips; forming a dielectric layer on regions between the solder pads of any two adjacent ones of the chips ; forming a metal layer on the dielectric layer electrically connected to the solder pads and forming a connective layer on the metal layer, wherein the width of the connective layer is smaller than that of the metal layer; cutting along the grooves to break off the electrical connection between adjacent chips; thinning the non-active surface of the wafer to the extent that the metal layer is exposed from the wafer; and separating the chips to form a plurality of stackable semiconductor devices. Accordingly, a multi-chip stack structure can be obtained by stacking and electrically connecting a plurality of semiconductor devices through the electrical connection between the connective layer of a semiconductor device and the metal layer of another semiconductor device, thereby effectively integrating more chips without having to increase the stacking area, and further the problems of poor electrical connection, complicated manufacturing processes and high costs known in the prior art can be avoided.

摘要翻译： 公开了一种可堆叠半导体器件及其制造方法。 该方法包括提供由多个芯片组成的晶片，其中在每个芯片的有源表面上形成多个焊盘，并且在任何两个相邻芯片的焊盘之间形成多个沟槽; 在任何两个相邻芯片的焊盘之间的区域上形成电介质层; 在与所述焊料焊盘电连接的所述电介质层上形成金属层，并在所述金属层上形成连接层，其中所述连接层的宽度小于所述金属层的宽度; 沿着凹槽切割以破坏相邻芯片之间的电连接; 使晶片的非活性表面变薄至金属层从晶片露出的程度; 并分离所述芯片以形成多个可堆叠半导体器件。 因此，通过半导体器件的连接层与另一半导体器件的金属层之间的电连接层叠并电连接多个半导体器件，可以获得多芯片堆叠结构，从而有效地集成更多的芯片，而不必 增加堆积面积，进一步避免了现有技术中已知的电连接不良，制造工艺复杂，成本高的问题。

公开(公告)号：US07423340B2

公开(公告)日：2008-09-09

申请号：US11112107

申请日：2005-04-21

申请人： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L23/053 ,  H01L23/12 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28 ,  H01L23/02

CPC分类号： H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.