公开(公告)号：US09613869B2

公开(公告)日：2017-04-04

申请号：US15182048

申请日：2016-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L21/331 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L21/823481 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/785

Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

公开(公告)号：US09607900B1

公开(公告)日：2017-03-28

申请号：US14850154

申请日：2015-09-10

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L27/01 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L29/66 ,  H01L21/283 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/201

CPC classification number: H01L21/823807 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0226 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/201 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.

公开(公告)号：US20170076990A1

公开(公告)日：2017-03-16

申请号：US14850154

申请日：2015-09-10

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/306 ,  H01L29/201 ,  H01L21/283 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0226 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/201 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.

Abstract translation: 提供了形成紧密堆积的混合纳米线的技术。 一方面，用于形成混合纳米线的方法包括：在基板上的叠层中形成第一和第二材料的交替层; 在堆叠中形成第一沟槽和第二沟槽; 在所述第一沟槽内横向蚀刻所述第二材料的层以在所述层中形成第一空腔; 在填充第一空腔的第一沟槽内生长第一外延材料; 在所述第二沟槽内横向蚀刻所述第二材料的层以在所述层中形成第二空腔; 在填充第二空腔的第二沟槽内生长第二外延材料，其中第一空腔中的第一外延材料和第二空腔中的第二外延材料是混合纳米线。 还提供了纳米线FET器件及其形成方法。

公开(公告)号：US20170062601A1

公开(公告)日：2017-03-02

申请号：US14843321

申请日：2015-09-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/268 ,  H01L21/225 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L29/66636 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/2251 ,  H01L21/268 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure. The epitaxial semiconductor material includes a first portion having a substantially conformal thickness on a lower portion of the fin structure sidewall and a second portion having a substantially diamond shape that is present on an upper surface of the source portion and drain portion of the fin structure. A spacer present on first portion of the epitaxial semiconductor material.

Abstract translation: 一种半导体器件，其包括存在于鳍结构的沟道部分上的至少一个翅片结构和栅极结构。 外延半导体材料存在于翅片结构上的源极区域和漏极区域中的至少一个上。 外延半导体材料包括在翅片结构侧壁的下部具有基本上共形厚度的第一部分和具有基本上菱形形状的第二部分，该第二部分存在于鳍部结构的源极部分和漏极部分的上表面上。 存在于外延半导体材料的第一部分上的间隔物。

公开(公告)号：US20170062592A1

公开(公告)日：2017-03-02

申请号：US15350065

申请日：2016-11-13

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/267 ,  H01L21/225 ,  H01L21/265 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8252 ,  H01L21/324

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/2258 ,  H01L21/26513 ,  H01L21/3228 ,  H01L21/324 ,  H01L21/3245 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8252 ,  H01L21/8256 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/66446 ,  H01L29/66522 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

公开(公告)号：US09576980B1

公开(公告)日：2017-02-21

申请号：US14830868

申请日：2015-08-20

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L21/28 ,  H01L29/51 ,  H01L21/8234

CPC classification number: H01L21/845 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

Abstract: FinFET devices are formed on the same semiconductor structure wherein at least one finFET device has a gate dielectric structure that is different in thickness relative to a gate dielectric structure of at least one other finFET device. The finFET devices are formed as part of the same fabrication process.

Abstract translation: FinFET器件形成在相同的半导体结构上，其中至少一个finFET器件具有相对于至少一个其它finFET器件的栅极电介质结构的厚度不同的栅极电介质结构。 finFET器件形成为相同制造工艺的一部分。

公开(公告)号：US09570591B1

公开(公告)日：2017-02-14

申请号：US14966171

申请日：2015-12-11

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus Standaert ,  Junli Wang

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/28 ,  H01L21/283

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66553

Abstract: A method for fabricating a semiconductor device comprises forming active regions on a semiconductor substrate, forming a gate stack over the active regions and regions adjacent to the active regions, depositing a layer of conductive material over the active regions and the substrate, patterning a first mask over the conductive material, etching to remove exposed portions of the conductive material and form conductive contacts, patterning a second mask over portions of the gate stacks and conductive contacts, and etching to remove exposed portions of the gate stack.

公开(公告)号：US09570574B1

公开(公告)日：2017-02-14

申请号：US15180171

申请日：2016-06-13

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Veeraraghavan S. Basker ,  Huiming Bu ,  Zuoguang Liu

IPC: H01L21/768 ,  H01L29/45 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/535

CPC classification number: H01L29/45 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66795

Abstract: A method of fabricating a contact above a source or drain region of an integrated circuit includes depositing a first liner conformally in a bottom and along a sidewall of a trench formed above the source or drain region, depositing a second liner conformally over the first liner, and stripping the first liner and the second liner from a portion of the sidewall from an opening of the trench to a height above the bottom of the trench. The method also includes depositing a third liner conformally over the second liner on the bottom and to the height above the bottom of the trench and on the portion of the sidewall, and depositing a metal fill to fill the trench.

Abstract translation: 一种在集成电路的源极或漏极区域上制造接触的方法包括：在底部和沿着形成在源极或漏极区域上方的沟槽的侧壁上共形沉积第一衬垫，在第一衬里上共形沉积第二衬垫， 以及从所述沟槽的开口的所述侧壁的一部分剥离所述第一衬垫和所述第二衬垫到所述沟槽的底部之上的高度。 该方法还包括将第三衬套在底部上平行地沉积在第二衬垫上方并且在沟槽的底部上方和在侧壁的部分上方的高度沉积，并且沉积金属填充物以填充沟槽。

公开(公告)号：US09570571B1

公开(公告)日：2017-02-14

申请号：US14944436

申请日：2015-11-18

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L29/43 ,  H01L27/06 ,  H01L27/07 ,  H01L49/02 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/0629 ,  H01L21/0273 ,  H01L21/31051 ,  H01L21/32051 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L23/5226 ,  H01L23/535 ,  H01L27/0288 ,  H01L27/0635 ,  H01L27/0738 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/401 ,  H01L29/4238 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/66545

Abstract: Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate stack having a self-aligning cap and a gate metal on a substrate, depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed. Additionally, methods include removing the self-aligning cap and the gate metal from the exposed gate stack, depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack, and forming a bar contact and contact via above the metal resistor.

Abstract translation: 这里描述的是半导体器件及其形成方法。 在一些方面，形成半导体器件的方法包括在衬底上形成具有自对准盖和栅极金属的栅极堆叠，在半导体器件上沉积抗蚀剂掩模，以及对抗蚀剂掩模进行构图，使得栅极堆叠暴露 。 此外，方法包括从暴露的栅极堆叠中去除自对准盖和栅极金属，在半导体器件上沉积电阻器金属，使得在暴露的栅极堆叠内形成金属电阻器，并且通过上述形成条形接触和接触 金属电阻。

公开(公告)号：US09559191B2

公开(公告)日：2017-01-31

申请号：US14578842

申请日：2014-12-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66803 ,  H01L21/225 ,  H01L21/265 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76895 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Abstract translation: 一种形成半导体器件的方法，包括从体半导体衬底形成翅片结构并形成与翅片结构的侧壁的下部接触的隔离区域，其中鳍结构的侧壁的上部被暴露。 在翅片结构的侧壁的上部形成牺牲隔离物。 隔离区域是凹进的，以提供翅片结构的侧壁的暴露部分。 掺杂半导体材料形成在翅片结构的侧壁的下部的暴露部分上。 掺杂剂从掺杂半导体材料扩散到鳍结构的基底部分。