公开(公告)号：US08980765B2

公开(公告)日：2015-03-17

申请号：US13656483

申请日：2012-10-19

Applicant: Intermolecular, Inc.

Inventor： Sunil Shanker ,  Tony P. Chiang

IPC: H01L21/31 ,  H01J37/32 ,  C23C16/04 ,  C23C16/455 ,  C23C16/509

CPC classification number: C23C16/047 ,  C23C16/04 ,  C23C16/45536 ,  C23C16/45551 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/45591 ,  C23C16/4583 ,  C23C16/46 ,  C23C16/50 ,  C23C16/5096 ,  C23C16/52 ,  H01J37/32357 ,  H01J37/32366

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract translation: 描述组合等离子体增强沉积技术，包括指定衬底的多个区域，为多个区域的至少第一区域提供前体，以及向第一区域提供等离子体，以将第一材料沉积在使用 第一前体，其中所述第一材料不同于形成在所述基底的第二区域上的第二材料。

公开(公告)号：US08980744B2

公开(公告)日：2015-03-17

申请号：US13675852

申请日：2012-11-13

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Toshiyuki Hirota ,  Pragati Kumar ,  Xiangxin Rui ,  Sunil Shanker

IPC: H01L27/108 ,  H01L49/02 ,  C23C16/40

CPC classification number: H01L28/60 ,  C23C16/405 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Abstract translation: 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。

公开(公告)号：US08980682B2

公开(公告)日：2015-03-17

申请号：US14133203

申请日：2013-12-18

Applicant: Intermolecular Inc.

Inventor： Haifan Liang ,  Jeroen Van Duren

IPC: H01L21/00 ,  H01L31/0224 ,  H01L31/18

CPC classification number: H01L31/022466 ,  H01L31/0747 ,  H01L31/1832 ,  H01L31/1884 ,  Y02E10/50

Abstract: Methods of forming absorber layers in a TFPV device are provided. Methods are described to provide the formation of metal oxide films and heating the metal oxide films in the presence of a chalcogen to form a metal-oxygen-chalcogen alloy. Methods are described to provide the formation of metal oxide films, forming a layer of elemental chalcogen on the metal oxide film, and heating the stack to form a metal-oxygen-chalcogen alloy. In some embodiments, the metal oxide film includes zinc oxide and the chalcogen includes selenium.

Abstract translation: 提供了在TFPV装置中形成吸收层的方法。 描述了提供金属氧化物膜的形成和在硫族元素存在下加热金属氧化物膜以形成金属 - 氧 - 硫族元素合金的方法。 描述了形成金属氧化物膜的方法，在金属氧化物膜上形成元素硫族元素层，并加热该叠层以形成金属 - 氧 - 硫族元素合金。 在一些实施方案中，金属氧化物膜包括氧化锌，硫族元素包括硒。

公开(公告)号：US08973524B2

公开(公告)日：2015-03-10

申请号：US13685961

申请日：2012-11-27

Applicant: Intermolecular, Inc.

Inventor： Richard R. Endo ,  Rajesh Kelekar

IPC: B05C11/11 ,  B05C11/115 ,  B05D1/00 ,  B05D1/32

CPC classification number: B05D1/005 ,  B05D1/32

Abstract: A spin deposition apparatus includes a deposition mask configured to be arranged proximate a target substrate. The deposition mask includes at least one fluid reservoir offset from a rotational axis of the deposition mask and configured to hold fluid for dispersal on a portion of a surface of the target substrate.

Abstract translation: 旋转沉积设备包括被配置为邻近目标衬底设置的沉积掩模。 沉积掩模包括从沉积掩模的旋转轴线偏移的至少一个流体储存器，并且构造成保持用于分散在目标基板的表面的一部分上的流体。

公开(公告)号：US08962354B2

公开(公告)日：2015-02-24

申请号：US14491407

申请日：2014-09-19

Applicant: Intermolecular, Inc.

Inventor： Monica Mathur ,  Michael Miller ,  Prashant B. Phatak

IPC: H01L21/66 ,  H01L49/02 ,  C23C14/22 ,  C23C16/455 ,  H01L29/51

CPC classification number: H01L28/40 ,  C23C14/228 ,  C23C16/45525 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/517

Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.

Abstract translation: 形成层的方法可以包括在衬底上限定多个离散位置隔离区（SIR），在离散SIR之一上形成第一层，在第一层上形成第二层，测量晶格参数或电性质 用于形成第一层的工艺参数以不同离散SIR之间的组合方式变化，以探索可能导致对期望晶体结构的第二层的适当晶格匹配的可能层。

公开(公告)号：US08961814B2

公开(公告)日：2015-02-24

申请号：US14132383

申请日：2013-12-18

Applicant: Intermolecular Inc.

Inventor： Jeroen Van Duren ,  Zhi-Wen Wen Sun

IPC: C09K13/00 ,  C09K13/04 ,  C09K13/08 ,  C09K13/06 ,  C09K13/02 ,  H01L21/306 ,  H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L21/465 ,  H01L21/70

CPC classification number: H01L21/30604 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/32134 ,  H01L21/465 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: Methods and formulations for the selective etching of etch stop layers deposited above metal-based semiconductor layers used in the manufacture of TFT-based display devices are presented. The formulations are based on an alkaline solution. Methods and formulations for the selective etching of molybdenum-based and/or copper-based source/drain electrode layers deposited above metal-based semiconductor layers used in the manufacture of TFT-based display devices are presented. The formulations are based on an alkaline solution.

Abstract translation: 提出了用于选择性蚀刻沉积在制造TFT基显示器件中的金属基半导体层之上的蚀刻停止层的方法和配方。 制剂基于碱性溶液。 提出了用于选择性蚀刻沉积在制造TFT基显示装置中的金属基半导体层之上的钼基和/或铜基源/漏电极层的方法和配方。 制剂基于碱性溶液。

公开(公告)号：US20150035085A1

公开(公告)日：2015-02-05

申请号：US14109728

申请日：2013-12-17

Applicant: Intermolecular Inc.

Inventor： Khaled Ahmed ,  Frank Greer

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/02181 ,  C23C16/405 ,  C23C16/45531 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

Abstract: Embodiments provided herein describe high-k dielectric layers and methods for forming high-k dielectric layers. A substrate is provided. The substrate includes a semiconductor material. The substrate is exposed to a hafnium precursor. The substrate is exposed to a zirconium precursor. The substrate is exposed to an oxidant only after the exposing of the substrate to the hafnium precursor and the exposing of the substrate to the zirconium precursor. The exposing of the substrate to the hafnium precursor, the exposing of the substrate to the zirconium precursor, and the exposing of the substrate to the oxidant causes a layer to be formed over the substrate. The layer includes hafnium, zirconium, and oxygen.

Abstract translation: 本文提供的实施例描述了高k电介质层和用于形成高k电介质层的方法。 提供基板。 基板包括半导体材料。 将基底暴露于铪前体。 将基底暴露于锆前体。 只有在将基底暴露于铪前体并将基底暴露于锆前体之后，才将基底暴露于氧化剂。 将衬底暴露于铪前体，将衬底暴露于锆前体，以及将衬底暴露于氧化剂引起在衬底上形成一层。 该层包括铪，锆和氧。

公开(公告)号：US20150034896A1

公开(公告)日：2015-02-05

申请号：US14488494

申请日：2014-09-17

Applicant: Intermolecular Inc.

Inventor： Pragati Kumar ,  Sean Barstow ,  Tony P. Chiang ,  Sandra G Malhotra

IPC: H01L45/00 ,  H01L29/861 ,  H01L27/24

CPC classification number: H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165

Abstract: Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

Abstract translation: 包括电阻开关金属氧化物的非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。

公开(公告)号：US08946015B2

公开(公告)日：2015-02-03

申请号：US14333715

申请日：2014-07-17

Applicant: Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

Inventor： Anh Duong ,  Clemens Fitz ,  Olov Karlsson

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/49

CPC classification number: C11D11/0047 ,  C11D7/04 ,  C11D7/08 ,  C11D7/265 ,  H01L21/02057 ,  H01L21/02068 ,  H01L21/28052 ,  H01L21/324 ,  H01L21/6704 ,  H01L29/4975 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66568

Abstract: A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract translation: 公开了一种在镍铂硅化过程中从半导体衬底中清除残余物的方法，包括多步残渣清洗，包括将底物暴露于王水溶液中，然后暴露于含有盐酸和过氧化氢的溶液中。 SC2溶液可以与剩余的铂残留物进一步反应，使其更易溶于水溶液，从而从基底表面溶解。

公开(公告)号：US08945952B2

公开(公告)日：2015-02-03

申请号：US14071894

申请日：2013-11-05

Applicant: Intermolecular Inc.

Inventor： John Foster

IPC: H01L21/66 ,  H01L21/302 ,  H01L21/461 ,  C23F1/00 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/8238

CPC classification number: H01L21/30604 ,  H01L21/02071 ,  H01L21/32134 ,  H01L21/67086 ,  H01L21/823828 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30

Abstract: Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.

Abstract translation: 提供了组合工作流程，用于在形成晶体管器件的栅极结构之后评估清洁过程，为栅极堆叠形成提供优化的工艺条件，包括使用高k电介质的金属栅极堆叠。 NMOS和PMOS晶体管器件组合地制造在衬底的多个区域上，每个区域暴露于不同的清洁化学和工艺。 然后对晶体管器件进行表征，并对数据进行比较，对不同清洁化学品和工艺的潜在损害进行分类。 可以获得优化的化学品和工艺以满足所需的装置要求。