公开(公告)号：US20190172921A1

公开(公告)日：2019-06-06

申请号：US16325333

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Van H. LE ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Shriram SHIVARAMAN

IPC: H01L29/45 ,  H01L29/786 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/443

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors. For instance, there is disclosed in accordance with one embodiment an oxide semiconductor transistor, having therein: a substrate layer; a channel layer formed atop the substrate; a metal gate and a gate oxide material formed atop the semiconducting oxide material of the channel layer; spacers positioned adjacent to the gate and gate oxide material; a dielectric layer formed atop the channel layer, the dielectric layer encompassing the spacers, the gate, and the gate oxide material; contact vias opened into the dielectric material forming an opening through the dielectric layer to the channel layer; a high mobility liner material lining the contact vias and in direct contact with the channel layer, the high mobility liner formed from a high mobility oxide material; and metallic contact material filling the contact vias opened into the dielectric material and separated from the channel layer by the high mobility liner of the contact vias. Other related embodiments are disclosed.

公开(公告)号：US20180323264A1

公开(公告)日：2018-11-08

申请号：US15773549

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Van H. LE ,  Rafael RIOS ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC

IPC: H01L29/24 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L21/443 ,  H01L29/04

CPC classification number: H01L29/24 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/443 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/12 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and an IGZO fin formed above the substrate. Embodiments may include a source contact and a drain contact that are formed adjacent to more than one surface of the IGZO fin. Additionally, embodiments may include a gate electrode formed between the source contact and the drain contact. The gate electrode may be separated from the IGZO layer by a gate dielectric. In one embodiment, the IGZO transistor is a fmfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20180315827A1

公开(公告)日：2018-11-01

申请号：US15770468

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Willy RACHMADY ,  Matthew V. METZ ,  Chandra S. MOHAPATRA ,  Gilbert DEWEY ,  Nadia M. RAHHAL-ORABI ,  Jack T. KAVALIEROS ,  Anand S. MURTHY

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/205 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28264 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.

公开(公告)号：US20180204947A1

公开(公告)日：2018-07-19

申请号：US15570742

申请日：2015-06-16

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Van H. LE ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Ashish AGRAWAL

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing sidewalls. The fin comprises a first semiconductor material. The subfin layer comprises a III-V semiconductor material.

公开(公告)号：US20170365681A1

公开(公告)日：2017-12-21

申请号：US15679077

申请日：2017-08-16

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Niloy MUKHERJEE ,  Matthew METZ ,  Jack T. KAVALIEROS ,  Nancy M. ZELICK ,  Robert S. CHAU

IPC: H01L29/51 ,  H01L21/285 ,  H01L21/324 ,  H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L29/49 ,  H01L23/485 ,  H01L29/78 ,  H01L45/00 ,  H01L33/40 ,  H01L33/00 ,  H01L31/0224 ,  H01L29/45 ,  H01L21/04 ,  H01L51/10 ,  H01L51/44 ,  H01L51/52 ,  H01B1/12

Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

公开(公告)号：US20170263708A1

公开(公告)日：2017-09-14

申请号：US15605795

申请日：2017-05-25

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Robert CHAU ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Matthew METZ ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L29/06 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02 ,  H01L21/225 ,  H01L21/283 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/04 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/20

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20170263706A1

公开(公告)日：2017-09-14

申请号：US15529481

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia M. RAHHAL-ORABI ,  Nancy M. ZELICK ,  Tahir GHANI

IPC: H01L29/06 ,  H01L29/04 ,  H01L29/205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0673 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.

公开(公告)号：US20170012125A1

公开(公告)日：2017-01-12

申请号：US15119345

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Van H. LE ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Ravi PILLARISETTY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Robert S. CHAU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823885 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

Abstract translation: 描述用于制造垂直半导体器件和纵向半导体器件的纵横比捕获（ART）方法。 例如，半导体器件包括具有第一晶格常数的最上表面的衬底。 第一源极/漏极区域设置在衬底的最上表面上并且具有第二不同的晶格常数。 垂直沟道区域设置在第一源极/漏极区域上。 第二源极/漏极区域设置在垂直沟道区域上。 栅堆叠设置在垂直沟道区的一部分上并完全环绕。

公开(公告)号：US20160276440A1

公开(公告)日：2016-09-22

申请号：US15037296

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Uygar E. Avci ,  Roza KOTLYAR ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Ian A. YOUNG

IPC: H01L29/12 ,  H01L29/205 ,  H01L29/165 ,  G11C5/06 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/125 ,  G11C5/06 ,  H01L29/0669 ,  H01L29/165 ,  H01L29/205 ,  H01L29/7391 ,  H01L29/7831

Abstract: Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage.

Abstract translation: 本文所述的本发明的实施例包括具有漏极区域，具有与漏极区域相反的导电类型的源极区域的沟道场效应晶体管（TFET），设置在源极区域和漏极区域之间的沟道区域，栅极设置在 沟道区域和设置在源区域和沟道区域的结点附近的异质袋。 异质袋包括不同于沟道区的半导体材料，并且包括小于沟道区中的带隙的隧穿势垒，并且在施加到栅极的电压时在通道区中形成量子阱以增加通过TFET晶体管的电流 门高于阈值电压。

公开(公告)号：US20160211263A1

公开(公告)日：2016-07-21

申请号：US14915185

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Niti GOEL ,  Robert S. CHAU ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Nancy M. ZELICK ,  Gilbert DEWEY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Ravi PILLARISETTY ,  Sansaptak DASGUPTA

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/205 ,  H01L21/8238 ,  H01L21/8252 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/785

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

Abstract translation: 从形成在浅沟槽隔离（STI）区域之间的一个或一对沟槽的底部的衬底表面外延生长单个鳍或一对共同组合的n型和p型单晶电子器件鳍。 翅片或翅片被图案化并且STI区域被蚀刻以形成在STI区域的蚀刻顶表面之上延伸的翅片或翅片的高度。 翅片高度可以是其宽度的至少1.5倍。 暴露的侧壁表面和每个翅片的顶表面用一个或多个共形外延材料外延包层以在翅片上形成器件层。 在生长翅片之前，可以从衬底表面生长毯式缓冲外延材料; 并且生长在STI沟槽中的翅片形成在覆盖层上方。 翅片的这种形成减少了材料界面晶格失配的缺陷。