公开(公告)号：US08946815B2

公开(公告)日：2015-02-03

申请号：US13959339

申请日：2013-08-05

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Venkatesan Ananthan

IPC: H01L29/772 ,  H01L29/78 ,  H01L27/108

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7827 ,  H01L29/7841

Abstract: The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays.

Abstract translation: 本发明包括含有U形半导体材料片的浮体晶体管结构。 U形有一对连接到中心部分的插脚。 每个插脚包含一对门控耦合的源极/漏极区域的源极/漏极区域，并且晶体管的浮体在中心部分内。 半导体材料切片可以位于前门和后门之间。 可以将浮体晶体管结构并入到存储器阵列中，这又可以并入到电子系统中。 本发明还包括形成浮体晶体管结构的方法，以及将浮体晶体管结构结合到存储器阵列中的方法。

公开(公告)号：US20140346613A1

公开(公告)日：2014-11-27

申请号：US14292443

申请日：2014-05-30

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Gordon Haller

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.

Abstract translation: 提供了用于制造翅片结构的翅片方法。 更具体地，翅片结构形成在基板中。 翅片结构可以包括由通道分开的两个翅片，其中翅片可以用作场效应晶体管的翅片。 翅片结构形成在衬底的上表面下方，并且可以在不利用光刻掩模来形成以蚀刻鳍片的情况下形成。

公开(公告)号：US20140273358A1

公开(公告)日：2014-09-18

申请号：US14287659

申请日：2014-05-27

Applicant: Micron Technology, Inc.

Inventor： John K. Zahurak ,  Sanh D. Tang ,  Lars P. Heineck ,  Martin C. Roberts ,  Wolfgang Mueller ,  Haitao Liu

IPC: H01L29/66 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L23/528 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2454 ,  H01L29/36 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7841 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed.

Abstract translation: 电路结构包括具有阵列区域和周边区域的基板。 阵列和外围区域中的衬底包括在第一半导体材料上的绝缘体材料，绝缘体材料上方的导电材料和导电材料上的第二半导体材料。 阵列区域包括包括第二半导体材料的垂直电路器件。 外围区域包括包括第二半导体材料的水平电路器件。 外围区域中的水平电路器件分别具有包括第二半导体材料的浮体。 外围区域中的导电材料在浮体的第二半导体材料的下面并电耦合。 阵列区域中的导电带在垂直电路装置下方。 导电带包括导电材料，并且单独地电耦合到阵列区域中的多个垂直电路器件。 公开了其他实现。

公开(公告)号：US20130307042A1

公开(公告)日：2013-11-21

申请号：US13952742

申请日：2013-07-29

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak ,  Werner Juengling

IPC: H01L27/108

CPC classification number: H01L27/10802 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/4236 ,  H01L29/7841

Abstract: Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.

Abstract translation: 包括浮置体细胞结构，其包括布置在背栅上的浮体阵列阵列和与后门间隔开的浮体细胞的源区和漏区。 浮体细胞可以各自包括体积的半导体材料，其具有在柱之间延伸的通道区域，其可以通过诸如U形沟槽的空隙分开。 阵列的浮体电池可以电耦合到另一个栅极，另一个栅极可以设置在半导体材料的体积的侧壁上或其内的空隙中。 还公开了形成浮体电池器件的方法。

公开(公告)号：US20130248800A1

公开(公告)日：2013-09-26

申请号：US13897615

申请日：2013-05-20

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L27/24 ,  H01L21/22

CPC classification number: H01L27/2409 ,  H01L21/22 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

Abstract: Non-volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different locations along a length of the electrode and may be spaced apart from adjacent diodes by a dielectric material. The electrode may electrically couple the diodes of the memory strings to one another and to another memory device, such as, a MOSFET device. Methods of forming the non-volatile memory devices as well as intermediate structures are also disclosed.

Abstract translation: 包括包括多个垂直叠加的二极管的存储器串的非易失性存储器件。 每个二极管可以沿着电极的长度布置在不同的位置处，并且可以通过介电材料与相邻的二极管间隔开。 电极可以将存储器串的二极管彼此电耦合到另一个存储器件，例如MOSFET器件。 还公开了形成非易失性存储器件以及中间结构的方法。

公开(公告)号：US20130230957A1

公开(公告)日：2013-09-05

申请号：US13865117

申请日：2013-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Robert J. Hanson ,  Sanh D. Tang

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7834

Abstract: The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括形成场效应晶体管的方法。 在一个实施方案中，本发明包括在衬底上形成场效应晶体管的方法，其中场效应晶体管包括一对导电掺杂的源极/漏极区域，在该对源极/漏极区域之间接收的沟道区域，以及 晶体管栅极可靠地接收在沟道区域。 这种实现包括在沉积材料之前对该对源极/漏极区进行掺杂剂激活退火，从而制造晶体管栅极的导电部分。 考虑了其他方面和实现。

公开(公告)号：US20130170284A1

公开(公告)日：2013-07-04

申请号：US13777083

申请日：2013-02-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sanh D. Tang ,  Gurtej S. Sandhu

IPC: G11C13/00

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  G11C2213/78 ,  H01L27/0688 ,  H01L27/101

Abstract: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

Abstract translation: 垂直堆叠层的非易失性交叉点存储单元的阵列包括在存储单元的各个层内的多个水平取向的字线。 具有局部垂直位线延伸的多个水平定向的全局位线延伸穿过多个层。 存储单元的个体包括在水平定向的字线之一和本地垂直位线延伸之一中的一个之间接收的多电阻状态材料，其中这些交叉具有这样的交叉的单个存储器单元的相对的导电电极。 多个位线选择电路单独地电和物理地连接到本地垂直位线延伸的个体，并且被配置为向全局水平位线的个体提供电压电位。 公开了其它实施例和方面。

公开(公告)号：US20250151264A1

公开(公告)日：2025-05-08

申请号：US19013180

申请日：2025-01-08

Applicant: Micron Technology, Inc.

Inventor： Hong Li ,  Ramaswamy Ishwar Venkatanarayanan ,  Sanh D. Tang ,  Erica L. Poelstra

IPC: H10B12/00 ,  G11C11/402 ,  H01L23/49 ,  H01L23/538 ,  H10D30/01 ,  H10D30/63

Abstract: Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.

公开(公告)号：US11923289B2

公开(公告)日：2024-03-05

申请号：US17837923

申请日：2022-06-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  G11C13/00 ,  H01L23/528 ,  H01L27/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B63/00 ,  H10N70/00

CPC classification number: H01L23/52 ,  G11C13/0007 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35 ,  H10B63/845 ,  H10N70/8822 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/8833 ,  H10N70/8836 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L2924/0002 ,  H10B41/35 ,  H10N70/882 ,  H10N70/883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

公开(公告)号：USRE49715E1

公开(公告)日：2023-10-24

申请号：US17463420

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Martin C. Roberts ,  Sanh D. Tang ,  Fred D. Fishburn

IPC: H01L29/08 ,  H10B12/00 ,  H10B53/20 ,  H01L23/528 ,  H10B53/10 ,  H01L29/10 ,  H10B53/30 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/06 ,  H01L21/306 ,  H01L21/28 ,  H01L49/02

CPC classification number: H01L29/0847 ,  H01L23/528 ,  H01L28/60 ,  H01L29/1033 ,  H01L29/42376 ,  H10B12/03 ,  H10B12/05 ,  H10B12/30 ,  H10B12/48 ,  H10B12/50 ,  H10B53/10 ,  H10B53/20 ,  H10B53/30 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28035 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/32134 ,  H01L27/0688

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. Additional embodiments are disclosed.