公开(公告)号：US20180090504A1

公开(公告)日：2018-03-29

申请号：US15280587

申请日：2016-09-29

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

IPC分类号： H01L27/112 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234

CPC分类号： H01L27/11273 ,  H01L21/823475 ,  H01L21/823487 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/7827

摘要： A mask programmable read-only memory (PROM) cell is provided utilizing a vertical transistor processing flow. PROM programming is performed during the processing flow itself. Notably, “0” or “1” state can be programmed by tuning the threshold voltage of the vertical transistor by controlling the doping concentration of the epitaxially grown semiconductor channel material.

公开(公告)号：US09929253B2

公开(公告)日：2018-03-27

申请号：US15178853

申请日：2016-06-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

发明人： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

摘要： A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

公开(公告)号：US09917195B2

公开(公告)日：2018-03-13

申请号：US14812425

申请日：2015-07-29

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

发明人： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L29/76 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/306

CPC分类号： H01L29/1033 ,  H01L21/30621 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

公开(公告)号：US09911740B2

公开(公告)日：2018-03-06

申请号：US15208495

申请日：2016-07-12

申请人： GLOBALFOUNDRIES INC.

发明人： David Paul Brunco ,  Jeffrey Bowman Johnson

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L21/265 ,  H01L21/762 ,  H01L21/225 ,  H01L21/02 ,  H01L29/167 ,  H01L21/8238 ,  H01L29/10

CPC分类号： H01L27/0924 ,  H01L21/02529 ,  H01L21/2251 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/167

摘要： Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.

公开(公告)号：US20180061989A1

公开(公告)日：2018-03-01

申请号：US15685040

申请日：2017-08-24

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Yuta ENDO

IPC分类号： H01L29/786 ,  H01L29/10 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7869 ,  H01L21/823412 ,  H01L27/088 ,  H01L27/1225 ,  H01L29/1033 ,  H01L29/78648 ,  H01L29/78696

摘要： A high-performance semiconductor device with high reliability is provided. The semiconductor device includes a first transistor, a second transistor, a first metal oxide covering at least part of the first transistor, an insulating film over the first transistor and the second transistor, and a second metal oxide over the insulating film. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide, a first source electrode, a first drain electrode, a second gate insulating film, and a second gate electrode. The second transistor includes a third gate electrode, a third gate insulating film, a second oxide, a second source electrode, a second drain electrode, a fourth gate insulating film, and a fourth gate electrode. The first gate insulating film and the second gate insulating film are in contact with the first metal oxide.

公开(公告)号：US20180061630A1

公开(公告)日：2018-03-01

申请号：US15684753

申请日：2017-08-23

申请人： Quora Technology, Inc.

发明人： Vladimir Odnoblyudov ,  Dilip Risbud ,  Ozgur Aktas ,  Cem Basceri

IPC分类号： H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/872 ,  H01L29/66 ,  H01L29/778 ,  C30B29/06 ,  C30B29/40 ,  C30B25/18

CPC分类号： H01L21/6835 ,  C30B25/183 ,  C30B29/06 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/02428 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/28264 ,  H01L21/4807 ,  H01L21/762 ,  H01L29/1033 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66143 ,  H01L29/66204 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/872 ,  H01L2221/68345 ,  H01L2221/6835

摘要： A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

公开(公告)号：US09905672B2

公开(公告)日：2018-02-27

申请号：US15276784

申请日：2016-09-26

申请人： Samsung Electronics Co., Ltd.

发明人： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Dharmendar Reddy Palle ,  Joon Goo Hong

IPC分类号： H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/04

CPC分类号： H01L29/66553 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0259 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78

摘要： A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.

公开(公告)号：US20180047846A1

公开(公告)日：2018-02-15

申请号：US15730542

申请日：2017-10-11

申请人： INTEL CORPORATION

发明人： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC分类号： H01L29/78 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H04B1/3827 ,  H01L29/06 ,  H01L29/10 ,  H01L29/267

CPC分类号： H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

公开(公告)号：US20180040730A1

公开(公告)日：2018-02-08

申请号：US15606937

申请日：2017-05-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Isaac Lauer ,  Jiaxing Liu ,  Renee T. Mo

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/10

CPC分类号： H01L29/7843 ,  H01L21/0217 ,  H01L21/02428 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/845 ,  H01L29/1033 ,  H01L29/66568 ,  H01L29/66818

摘要： A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

公开(公告)号：US20180026127A1

公开(公告)日：2018-01-25

申请号：US15625178

申请日：2017-06-16

申请人： HITACHI, LTD.

发明人： Takahiro MORIKAWA ,  Naoki WATANABE ,  Hiroyuki YOSHIMOTO

IPC分类号： H01L29/78 ,  H01L21/04 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L21/047 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66712

摘要： A semiconductor device has an active region in which a plurality of unit cells are regularly arranged, each of the unit cells including: a channel region having a first conductivity type and formed over a front surface of a semiconductor substrate; a source region having a second conductivity type different from the first conductivity type and formed over the front surface of the semiconductor substrate in such a manner as to be in contact with the channel region; and a JFET region having the second conductivity type and is formed over the front surface of the semiconductor substrate on the opposite side of the channel region from the source region in such a manner as to be in contact with the channel region. The channel region is comprised of a first channel region and a second channel region higher than the first channel region in impurity concentration, over the front surface of the semiconductor substrate.