公开(公告)号：US12124035B2

公开(公告)日：2024-10-22

申请号：US17182016

申请日：2021-02-22

Applicant: Adeia Semiconductor Technologies LLC

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Gabriel Z. Guevara ,  Min Tao

IPC: H01L21/78 ,  G02B27/01

CPC classification number: G02B27/0172 ,  G02B2027/0134 ,  G02B2027/015 ,  G09G2370/18

Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.

公开(公告)号：US12094835B2

公开(公告)日：2024-09-17

申请号：US18377706

申请日：2023-10-06

Applicant: Adeia Semiconductor Technologies LLC

Inventor： Shaowu Huang ,  Javier A. Delacruz

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/566 ,  H01L23/3121 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025

Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

公开(公告)号：US20240250071A1

公开(公告)日：2024-07-25

申请号：US18379990

申请日：2023-10-13

Applicant: Adeia Semiconductor Technologies LLC

Inventor： Javier A. DeLaCruz ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L25/065 ,  G06F15/76 ,  G06F15/78 ,  H01L23/00 ,  H01L23/532 ,  H01L25/18

CPC classification number: H01L25/0657 ,  G06F15/7825 ,  H01L23/53204 ,  H01L24/08 ,  H01L24/83 ,  H01L25/18 ,  G06F2015/763 ,  H01L2224/08145 ,  H01L2225/06524 ,  H01L2924/1433 ,  H01L2924/1434

Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

公开(公告)号：US12027487B2

公开(公告)日：2024-07-02

申请号：US18145310

申请日：2022-12-22

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05684 ,  H01L2224/11009 ,  H01L2224/11464 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13084 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13655 ,  H01L2224/13684 ,  H01L2224/13686 ,  H01L2224/13805 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13844 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16265 ,  H01L2224/16268 ,  H01L2224/16501 ,  H01L2224/2919 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81026 ,  H01L2224/81065 ,  H01L2224/81099 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/83026 ,  H01L2224/83815 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3841

Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

公开(公告)号：US11824046B2

公开(公告)日：2023-11-21

申请号：US17583872

申请日：2022-01-25

Applicant: Adeia Semiconductor Technologies LLC

Inventor： Javier A. DeLaCruz ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L25/18 ,  G06F15/78 ,  H01L23/532 ,  H01L25/065 ,  H01L23/00 ,  G06F15/76

CPC classification number: H01L25/0657 ,  G06F15/7825 ,  H01L23/53204 ,  H01L24/08 ,  H01L24/83 ,  H01L25/18 ,  G06F2015/763 ,  H01L2224/08145 ,  H01L2225/06524 ,  H01L2924/1433 ,  H01L2924/1434

Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

公开(公告)号：US20230335531A1

公开(公告)日：2023-10-19

申请号：US18145310

申请日：2022-12-22

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/17 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/11 ,  H01L24/80 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/81026 ,  H01L2224/83026 ,  H01L2224/16501 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2224/16148 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2225/06513 ,  H01L2224/80895 ,  H01L2224/13684 ,  H01L2224/13562 ,  H01L2224/13844 ,  H01L2224/05605 ,  H01L2224/8181 ,  H01L2224/0401 ,  H01L2224/81193 ,  H01L2224/05611 ,  H01L2224/81065 ,  H01L2224/13655 ,  H01L2224/03009 ,  H01L2224/05639 ,  H01L2224/13847 ,  H01L2224/80896 ,  H01L2224/16268 ,  H01L2224/81099 ,  H01L2224/16238 ,  H01L2224/05684 ,  H01L2224/13805 ,  H01L2224/11464 ,  H01L2224/13018 ,  H01L2224/13686 ,  H01L2224/05572 ,  H01L2224/13019 ,  H01L2224/05616 ,  H01L2224/13084 ,  H01L2224/13809 ,  H01L2224/2919 ,  H01L2224/13564 ,  H01L2224/05644 ,  H01L2224/13855 ,  H01L2224/05609 ,  H01L2224/13811 ,  H01L2224/11009 ,  H01L2224/05571 ,  H01L2224/80357 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/3841 ,  H01L2224/16265

Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

公开(公告)号：US11715730B2

公开(公告)日：2023-08-01

申请号：US17327169

申请日：2021-05-21

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Min Tao ,  Liang Wang ,  Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L25/16 ,  H01L33/00 ,  H01L25/10 ,  H01L27/12 ,  H01L27/15 ,  H01L25/18 ,  H01L21/321 ,  H01L21/02 ,  H01L23/00 ,  H01L33/06 ,  H01L33/32 ,  H01L33/44 ,  H01L33/46 ,  H01L33/62

CPC classification number: H01L25/167 ,  H01L21/02118 ,  H01L21/3212 ,  H01L24/08 ,  H01L24/80 ,  H01L25/105 ,  H01L25/18 ,  H01L27/1214 ,  H01L27/156 ,  H01L33/007 ,  H01L33/0093 ,  H01L33/06 ,  H01L33/32 ,  H01L33/44 ,  H01L33/46 ,  H01L33/62 ,  H01L2224/08145 ,  H01L2224/80013 ,  H01L2224/80355 ,  H01L2224/80357 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/0066

Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

公开(公告)号：US11710718B2

公开(公告)日：2023-07-25

申请号：US17140519

申请日：2021-01-04

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05684 ,  H01L2224/11009 ,  H01L2224/11464 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13084 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13655 ,  H01L2224/13684 ,  H01L2224/13686 ,  H01L2224/13805 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13844 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16265 ,  H01L2224/16268 ,  H01L2224/16501 ,  H01L2224/2919 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81026 ,  H01L2224/81065 ,  H01L2224/8181 ,  H01L2224/81099 ,  H01L2224/81193 ,  H01L2224/83026 ,  H01L2224/83815 ,  H01L2225/06513 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3841 ,  H01L2224/13655 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13684 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05616 ,  H01L2924/00014 ,  H01L2224/05605 ,  H01L2924/00014 ,  H01L2224/05609 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/13811 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13809 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13805 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13847 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13855 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13844 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2224/05572 ,  H01L2924/00012

Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

公开(公告)号：US20250033138A1

公开(公告)日：2025-01-30

申请号：US18601402

申请日：2024-03-11

Applicant: Adeia Semiconductor Technologies LLC

Inventor： Cyprian Emeka Uzoh

IPC: B23K20/02 ,  B23K20/00 ,  H01L21/48 ,  H01L21/50 ,  H01L21/768 ,  H01L23/00 ,  H01L23/10 ,  H01L23/48 ,  H01L23/49 ,  H01L23/498 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H05K13/04

Abstract: A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.

公开(公告)号：US20250022752A1

公开(公告)日：2025-01-16

申请号：US18444460

申请日：2024-02-16

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Cyprian Emeka Uzoh

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/00 ,  H01L23/532

Abstract: Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.