公开(公告)号：US07002249B2

公开(公告)日：2006-02-21

申请号：US10294423

申请日：2002-11-12

申请人： Thomas P. Duffy ,  John Ryan Goodfellow ,  Robert T. Carroll ,  Kevin J. Cote ,  Sampath K. V. Karikalan ,  Suresh Golwalkar

发明人： Thomas P. Duffy ,  John Ryan Goodfellow ,  Robert T. Carroll ,  Kevin J. Cote ,  Sampath K. V. Karikalan ,  Suresh Golwalkar

IPC分类号： H01L23/495 ,  H01L27/02 ,  H01L23/48

CPC分类号： H01L24/85 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49052 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  Y10S257/916 ,  H01L2924/01004 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45147 ,  H01L2924/0132 ,  H01L2924/2075 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00011

摘要： A semiconductor device package is disclosed which includes inter-digitated input and output bond wires configured to increase the negative mutual inductive coupling between the wires, thus reducing the overall parasitic inductance of the device. In one embodiment, the microelectronic component includes a semiconductor device coupled to a substrate, such as a lead frame, a first set of bond wires connected to the semiconductor device for providing current flow into the semiconductor device, and a second set of bond wires that are in a current loop with the first set of bond wires and are connected to the semiconductor device for providing current flow out of the semiconductor device, wherein the first and second set of bond wires are configured in an inter-digitated pattern to increase the magnitude of mutual inductive coupling between the first and second set of bond wires. In one embodiment, the semiconductor device comprises a single semiconductor chip and the lead frame comprises a Quad Flat No-Lead (QFN) lead frame. Other embodiments include multiple chips and/or multiple lead frames.

摘要翻译： 公开了一种半导体器件封装，其包括配置为增加导线之间的负互感耦合的数字化输入和输出接合线，从而减小器件的总体寄生电感。 在一个实施例中，微电子部件包括耦合到诸如引线框架的基板的半导体器件，连接到半导体器件的用于提供电流流入半导体器件的第一组接合线，以及第二组接合线， 与第一组接合线处于电流回路中并且连接到半导体器件，用于提供从半导体器件流出的电流，其中第一组和第二组接合线被配置为数字化的图案以增加幅度 的第一组和第二组接合线之间的互感耦合。 在一个实施例中，半导体器件包括单个半导体芯片，并且引线框架包括四边形扁平无引线（QFN）引线框架。 其他实施例包括多个芯片和/或多个引线框架。

公开(公告)号：US06960031B2

公开(公告)日：2005-11-01

申请号：US10325259

申请日：2002-12-19

申请人： Jonathan McFarland ,  Suresh Golwalkar ,  Sampath K. V. Karikalan ,  Kevin J. Cote ,  Wu Chun Chou

发明人： Jonathan McFarland ,  Suresh Golwalkar ,  Sampath K. V. Karikalan ,  Kevin J. Cote ,  Wu Chun Chou

IPC分类号： G02B6/42 ,  G02B6/38 ,  G02B6/36

CPC分类号： G02B6/4292 ,  G02B6/4249

摘要： An optical coupler for forming an optical connection between one or more two dimensional photonic array devices and an optical fiber and for forming an electrical connection between the two dimensional photonic array devices and a substrate, a system including the optical coupler and materials, and methods of forming the optical coupler and system are disclosed. The optical coupler includes a light transmission medium and electrical connectors, which are at least partially encapsulated. In addition, the device includes alignment guides configured to receive guide pins from a fiber optic connector, such that when the fiber optic connector is attached to the optical coupler, fibers of the ribbon align with the two dimensional photonic array device(s) via the light transmission medium.

摘要翻译： 一种用于在一个或多个二维光子阵列器件和光纤之间形成光连接并用于形成二维光子阵列器件和衬底之间的电连接的光耦合器，包括光耦合器和材料的系统，以及 公开了形成光耦合器和系统。 光耦合器包括光传输介质和至少部分封装的电连接器。 另外，该装置包括对准引导件，其被配置为从光纤连接器接收引导销，使得当光纤连接器附接到光耦合器时，带的光纤经由二维光子阵列器件经由 光传输介质。

公开(公告)号：US06903270B1

公开(公告)日：2005-06-07

申请号：US09638172

申请日：2000-08-11

申请人： Doug A. Hawks ,  Mark A. Kuhlman ,  Kevin J. Cote

发明人： Doug A. Hawks ,  Mark A. Kuhlman ,  Kevin J. Cote

IPC分类号： H01L21/56 ,  H01L23/31 ,  H05K5/06 ,  H01L23/28

CPC分类号： H01L21/565 ,  H01L23/3121 ,  H01L23/3142 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： Method and structure for securing a mold compound to a printed circuit board is disclosed. A through hole or a blind hole is fabricated in a printed circuit board adjacent to a die. The hole is then filled with a mold compound. The mold compound also surrounds and covers the die. The mold compound within the hole locks the mold compound to the surface of the printed circuit board. In one embodiment, a through hole or a blind hole is fabricated adjacent to a semiconductor die. The semiconductor die is attached to a layer of gold-plated copper on the printed circuit board. After the semiconductor die is attached to the layer of gold-plated copper on the printed circuit board, the semiconductor die is surrounded and covered by the mold compound and the fabricated hole is filled with the mold compound. The mold compound within the hole has good adhesion to the resin layer which constitutes the printed circuit board. This adhesion locks the mold compound securely to the surface of the printed circuit board.

摘要翻译： 公开了用于将模具化合物固定到印刷电路板的方法和结构。 在与模具相邻的印刷电路板中制造通孔或盲孔。 然后用模具化合物填充该孔。 模具化合物还包围并覆盖模具。 孔内的模具化合物将模具化合物锁定到印刷电路板的表面。 在一个实施例中，邻近半导体管芯制造通孔或盲孔。 半导体管芯附着在印刷电路板上的一层镀金铜上。 在半导体管芯附着在印刷电路板上的镀金铜层上之后，半导体管芯被模具化合物包围并覆盖，并且所制造的孔填充有模具化合物。 孔内的模具化合物对构成印刷电路板的树脂层具有良好的粘合性。 这种粘合将模具复合物牢固地锁定到印刷电路板的表面。

公开(公告)号：US06803665B1

公开(公告)日：2004-10-12

申请号：US10016309

申请日：2001-11-02

申请人： Mohamed A. Megahed ,  Kevin J. Cote ,  Hassan S. Hashemi

发明人： Mohamed A. Megahed ,  Kevin J. Cote ,  Hassan S. Hashemi

IPC分类号： H01L2348

CPC分类号： H01L24/85 ,  B23K20/004 ,  B23K20/007 ,  B23K2101/40 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/45 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48464 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/78301 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00015

摘要： According to an embodiment, a semiconductor die has a source bond pad and a destination bond pad attached to a top surface of the semiconductor die. A stud bump is situated on the destination bond pad. A bonding wire is then ball bonded to the source bond pad and thereafter stitch bonded to the stud bump on the destination bond pad. The bonding wire acts as an off-chip inductor or a portion of an off-chip inductor. In one embodiment a number of bonding-wires and on chip conductors are used to form an off-chip inductor. The inductance of the off-chip inductor can be adjusted or fine-tuned by adjusting a loop height of the one or more bonding wires used in the off-chip inductor. The inductance of the invention's off-chip inductor can also be adjusted by increasing or decreasing the number of bonding wires used to form the off-chip inductor.

摘要翻译： 根据实施例，半导体管芯具有附接到半导体管芯的顶表面的源极接合焊盘和目的接合焊盘。 目标接合垫上有一个螺柱凸块。 然后将接合线焊接到源极接合焊盘，然后将其接合到目的地接合焊盘上的螺柱凸块上。 接合线用作片外电感器或片外电感器的一部分。 在一个实施例中，使用多个接合线和片上导体来形成片外电感器。 片外电感器的电感可以通过调整片外电感器中使用的一个或多个接合线的环路高度来调节或微调。 也可以通过增加或减少用于形成片外电感器的接合线的数量来调节本发明片外电感器的电感。

公开(公告)号：US06867493B2

公开(公告)日：2005-03-15

申请号：US09894728

申请日：2001-06-28

申请人： Hassan S. Hashemi ,  Kevin J. Cote

发明人： Hassan S. Hashemi ,  Kevin J. Cote

IPC分类号： H01L23/12 ,  H01L23/36 ,  H01L23/367 ,  H01L23/498 ,  H01L23/64 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H01L23/34

CPC分类号： H01L23/645 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/20753 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： One disclosed embodiment comprises a substrate having a top surface for receiving two or more semiconductor dies. The disclosed embodiment further comprises a printed circuit board attached to a bottom surface of the substrate and at least one via in the substrate. The at least one via provides an electrical connection between a signal bond pad of a first semiconductor die and the printed circuit board. The at least one via provides an electrical connection between a first substrate bond pad and the printed circuit board. The first substrate bond pad is connected to the first signal bond pad of the first semiconductor die by a first signal bonding wire. The at least one via also provides an electrical connection between the first signal bond pad of the first semiconductor die and a first land that is electrically connected to the printed circuit board.

摘要翻译： 一个公开的实施例包括具有用于接收两个或更多个半导体管芯的顶表面的衬底。 所公开的实施例还包括附接到衬底的底表面和衬底中的至少一个通孔的印刷电路板。 所述至少一个通孔在第一半导体管芯的信号焊盘与印刷电路板之间提供电连接。 所述至少一个通孔在第一基板接合焊盘和印刷电路板之间提供电连接。 第一衬底接合焊盘通过第一信号接合线连接到第一半导体管芯的第一信号焊盘。 所述至少一个通孔还提供第一半导体管芯的第一信号接合焊盘与电连接到印刷电路板的第一焊盘之间的电连接。