公开(公告)号：US07002249B2

公开(公告)日：2006-02-21

申请号：US10294423

申请日：2002-11-12

申请人： Thomas P. Duffy ,  John Ryan Goodfellow ,  Robert T. Carroll ,  Kevin J. Cote ,  Sampath K. V. Karikalan ,  Suresh Golwalkar

发明人： Thomas P. Duffy ,  John Ryan Goodfellow ,  Robert T. Carroll ,  Kevin J. Cote ,  Sampath K. V. Karikalan ,  Suresh Golwalkar

IPC分类号： H01L23/495 ,  H01L27/02 ,  H01L23/48

CPC分类号： H01L24/85 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49052 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  Y10S257/916 ,  H01L2924/01004 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45147 ,  H01L2924/0132 ,  H01L2924/2075 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00011

摘要： A semiconductor device package is disclosed which includes inter-digitated input and output bond wires configured to increase the negative mutual inductive coupling between the wires, thus reducing the overall parasitic inductance of the device. In one embodiment, the microelectronic component includes a semiconductor device coupled to a substrate, such as a lead frame, a first set of bond wires connected to the semiconductor device for providing current flow into the semiconductor device, and a second set of bond wires that are in a current loop with the first set of bond wires and are connected to the semiconductor device for providing current flow out of the semiconductor device, wherein the first and second set of bond wires are configured in an inter-digitated pattern to increase the magnitude of mutual inductive coupling between the first and second set of bond wires. In one embodiment, the semiconductor device comprises a single semiconductor chip and the lead frame comprises a Quad Flat No-Lead (QFN) lead frame. Other embodiments include multiple chips and/or multiple lead frames.

摘要翻译： 公开了一种半导体器件封装，其包括配置为增加导线之间的负互感耦合的数字化输入和输出接合线，从而减小器件的总体寄生电感。 在一个实施例中，微电子部件包括耦合到诸如引线框架的基板的半导体器件，连接到半导体器件的用于提供电流流入半导体器件的第一组接合线，以及第二组接合线， 与第一组接合线处于电流回路中并且连接到半导体器件，用于提供从半导体器件流出的电流，其中第一组和第二组接合线被配置为数字化的图案以增加幅度 的第一组和第二组接合线之间的互感耦合。 在一个实施例中，半导体器件包括单个半导体芯片，并且引线框架包括四边形扁平无引线（QFN）引线框架。 其他实施例包括多个芯片和/或多个引线框架。

公开(公告)号：US20120101343A1

公开(公告)日：2012-04-26

申请号：US13276325

申请日：2011-10-19

申请人： Thomas P. Duffy ,  Gerald T. Harder ,  Kevin Mori

发明人： Thomas P. Duffy ,  Gerald T. Harder ,  Kevin Mori

IPC分类号： A61B1/06

CPC分类号： A61B5/489

摘要： A trans-illumination device includes at least first and second sets of LEDs of two or more different colors arranged in a light head placed against a patient's skin. The LEDs are mounted to a printed circuit board in the light head. An electronic control circuit is coupled to the light head by an electrical cable to selectively operate the LEDs in two or more user-selected modes, with the ability to adjust the relative intensities of the different colors to best suit the physiology of the patient. The light head may have a U-shape to surround an area of interest while providing ready access thereto. The light head may be used with a disposable, detachable cover having lenses for directing light from the LEDs into the patient's tissues.

摘要翻译： 透射照明装置包括布置在靠在患者皮肤上的光头中的至少第一组和第二组两种或多种不同颜色的LED。 LED安装在光头中的印刷电路板上。 电子控制电路通过电缆耦合到光头，以选择性地以两种或多种用户选择的模式操作LED，具有调整不同颜色的相对强度以最适合于患者生理学的能力。 光头可以具有U形以围绕感兴趣的区域，同时提供对其的准备访问。 光头可以与一次性可拆卸的盖一起使用，其具有用于将来自LED的光引导到患者组织中的透镜。

公开(公告)号：US06795009B2

公开(公告)日：2004-09-21

申请号：US10237903

申请日：2002-09-09

申请人： Thomas P. Duffy ,  Malay Trivedi ,  Kevin Mori

发明人： Thomas P. Duffy ,  Malay Trivedi ,  Kevin Mori

IPC分类号： H03M112

CPC分类号： H02M3/1584 ,  H02M3/157

摘要： Currents flowing in the various channels within a voltage regulator module (VRM) are suitably converted to digital equivalents that can be processed to control each module in a modular power supply. Functions that may be digitally implemented include current balancing between channels, current sharing between various modules in a power supply, and/or the like. By monitoring the current provided on each channel within a module, for example, a controller can determine an average current for the channels, which in turn can be used to identify and compensate for over- or under-production in any particular channel. Active voltage positioning techniques and overload protection may also be implemented using digital techniques.

摘要翻译： 在电压调节器模块（VRM）内的各种通道中流动的电流适当地转换为可被处理以控制模块化电源中的每个模块的数字等效电路。 可以数字实现的功能包括通道之间的电流平衡，电源中的各个模块之间的电流共享等等。 通过监视在模块内的每个通道上提供的电流，例如，控制器可以确定通道的平均电流，这又可以用于识别和补偿任何特定通道中的过度或不足的产生。 有源电压定位技术和过载保护也可以使用数字技术实现。

公开(公告)号：US5384690A

公开(公告)日：1995-01-24

申请号：US97544

申请日：1993-07-27

申请人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

发明人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

IPC分类号： H01R4/26 ,  H01R4/58 ,  H01R12/61 ,  H01R13/66 ,  H05K1/00 ,  H05K1/03 ,  H05K1/14 ,  H05K3/00 ,  H05K3/32 ,  H05K3/46 ,  H01R23/68

CPC分类号： H05K3/4635 ,  H01R12/613 ,  H01R13/665 ,  H05K3/462 ,  H01R4/26 ,  H01R4/58 ,  H05K1/0373 ,  H05K1/0393 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10159 ,  H05K3/328 ,  H05K3/4623 ,  H05K3/4641 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49179 ,  Y10T428/24917

摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.

摘要翻译： 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。 各个子组件的层压是通过与要层压的区域中的子组件之间的全氟化碳聚合物化学相容（可粘合）化学相容的低熔点粘合剂，以及任选的与化学不相容的高熔点掩模 可粘合到）在不想层压的区域中的子组件之间的全氟化碳聚合物。 加热组件叠层以选择性地在要层压的区域中进行粘合和层压，同时避免在不想层压的区域中层压。

公开(公告)号：US5055151A

公开(公告)日：1991-10-08

申请号：US393085

申请日：1989-08-09

申请人： Thomas P. Duffy

发明人： Thomas P. Duffy

IPC分类号： B29C41/28 ,  B29C41/32 ,  B29C43/00 ,  E01C5/20 ,  E02D17/20

CPC分类号： E02D17/202 ,  B29C41/28 ,  B29C41/32 ,  B29C43/006 ,  E01C5/20

摘要： A porous, filamentary mat has a plurality of layers that are in intimate face-to-face relation and that have portions of the confronting faces thereof bonded together to enable those layers to constitute a unitary, porous, filamentary mat. Each of the layers has a plurality of elongated filaments of thermoplastic material; and each of those filaments is arranged in an essentially horizontal attitude and is longer than the mat. Each of those filaments has a number of bends therein which cause portions of each filament to cross and to engage other portions of that filament; and those bends also cause portions of each filament to cross and to engage portions of one or more adjacent filaments. The crossing portions of each filament, and the crossing portions of adjacent filaments, are bonded together by initial thermal bonds that are subsequently enhanced; as by pressing together the adjacent crossing portions of the various filaments of the mat while they are in a tacky state, by applying additional heat to the initially-thermally-bonded filaments of the mat to cause the initial thermal bonds to form longer and deeper bond, or by applying both heat and pressure to those initial thermal bonds.

摘要翻译： 多孔的丝状垫具有多个彼此紧密的面对面关系的层，并且其相对面的部分结合在一起以使得这些层能够构成一体的，多孔的丝状垫。 每个层都具有多根细长的热塑性材料长丝; 并且这些细丝中的每一根被布置成基本水平的姿态并且比垫长。 这些细丝中的每一根都具有多个弯曲部，其中每个细丝的一部分交叉并接合该长丝的其它部分; 并且这些弯曲也使得每个细丝的部分交叉并接合一个或多个相邻细丝的部分。 每个细丝的交叉部分和相邻长丝的交叉部分通过随后增强的初始热粘结而结合在一起; 通过将毡的各种长丝的相邻交叉部分压在一起，同时将它们处于粘性状态时，通过向垫的初始热粘合长丝施加额外的热量，以使初始热粘合形成更长更深的粘结 ，或通过对这些初始热粘合施加热和压力。

公开(公告)号：US06674320B2

公开(公告)日：2004-01-06

申请号：US09978613

申请日：2001-10-16

申请人： Thomas P. Duffy ,  Yi Zhang ,  Malay Trivedi

发明人： Thomas P. Duffy ,  Yi Zhang ,  Malay Trivedi

IPC分类号： H03B100

CPC分类号： H01F29/14

摘要： A control system, method and apparatus is provided for an orthogonally variable inductor. A method and apparatus is also provided for voltage regulation. Regulation is provided without the use of Silicon devices, such as FET's, in the output current path. Efficient voltage regulation is provided via varying the inductance of a device in the output current path, and alternatively via varying the inductance and duty cycle. An orthogonal inductive device is provided to vary the inductance in the output current path. The orthogonal inductive device is an external H field device, a series method orthogonal flux device, or a combined core device. Furthermore, a variable inductor is also provided in filters, amplifiers, and oscillators.

摘要翻译： 提供了一种用于正交可变电感器的控制系统，方法和装置。 还提供了用于电压调节的方法和装置。 在输出电流路径中不使用诸如FET的硅器件提供调节。 通过改变输出电流路径中的器件的电感，或者通过改变电感和占空比来提供有效的电压调节。 提供正交感应装置以改变输出电流路径中的电感。 正交电感器件是外部H场器件，串联方法正交通量器件或组合核心器件。 此外，滤波器，放大器和振荡器中还提供可变电感器。

公开(公告)号：US06563294B2

公开(公告)日：2003-05-13

申请号：US10112738

申请日：2002-04-01

申请人： Thomas P. Duffy ,  Ryan Goodfellow ,  David Susak

发明人： Thomas P. Duffy ,  Ryan Goodfellow ,  David Susak

IPC分类号： G05F140

CPC分类号： H02M7/493 ,  H02J1/102 ,  H02M3/157 ,  H02M3/1584 ,  H02M2001/008

摘要： A highly phased power regulation (converter) system having an improved control feature is provided. A controller, such as a digital signal processor or microprocessor, receives digital information from a plurality of power conversion blocks and transmits control commands in response to the information. The controller is able to change the mode of operation of the system and/or re-phase the power blocks to accommodate a dynamic load requirement, occasions of high transient response or detection of a fault. In one embodiment, a microprocessor receives digital information and converted power from one or more power blocks. In this manner, the microprocessor is able to receive feedback on its own operation. The controller is also able to anticipate and predict conditions by analyzing precursor data. In this manner, the controller is able to modify the system as needed in anticipation of the forthcoming event.

公开(公告)号：US5395198A

公开(公告)日：1995-03-07

申请号：US901640

申请日：1992-06-19

申请人： Thomas P. Duffy ,  Lewis C. Hecht ,  Merritt P. Sulger, deceased ,  Ernst E. Thiele ,  Mark V. Pierson ,  Lawrence E. Williams

发明人： Thomas P. Duffy ,  Lewis C. Hecht ,  Merritt P. Sulger, deceased ,  Ernst E. Thiele ,  Mark V. Pierson ,  Lawrence E. Williams

IPC分类号： B23P21/00 ,  B25H3/02 ,  B65G49/07 ,  H01L21/00 ,  H01L21/673 ,  H01L21/677 ,  H01L21/683 ,  H05K3/00 ,  B65G49/06 ,  B65H1/00 ,  C23C16/00

CPC分类号： H01L21/67236 ,  H01L21/67126 ,  H01L21/67363 ,  H01L21/67376 ,  H01L21/67386 ,  H01L21/67772

摘要： Disclosed is a system for handling large area, in-process, circuit panel layers. The circuit panel layers are thin and flimsy, and require rigid support for certain processing steps. The system includes a peripheral frame fixture for surrounding and supporting the in process circuit panel layer, and a a loading chuck for mounting the in-process circuit panel layer in the peripheral frame fixture. The peripheral frame fixture includes a bottom plate having a central opening to expose the circuit panel layer, a top frame having a corresponding central opening to expose the opposite surface of the circuit panel layer, and a compressive apparatus, as screws, bolts, or the like, for applying a z axis compressive force to the bottom plate, the top frame, and a panel layer therebetween. Optionally, the fixture may include alignment pins or fiducials for aligning the bottom plate, a panel layer, and the top frame, and a robotic interface for a robotic arm to grasp and transfer the peripheral frame fixture. The system also includes a loading chuck for mounting the in-process circuit panel layer in the peripheral frame fixture. The loading chuck includes a peripheral edge for receiving the bottom plate of the peripheral frame fixture. This provides co-planarity of the in-process circuit panel layer, the bottom plate of the peripheral frame fixture, and the vacuum table. The vacuum table is within the area bounded by the peripheral edge of the loading chuck and the peripheral frame of the peripheral frame fixture, and is coplanar with them. The vacuum table includes slidable bearing surfaces, with vacuum apertures for drawing a vacuum to hold the panel in place, and slide actuators for moving the slidable bearing surfaces to apply x-y axis tension to a panel on the bearing surfaces.

摘要翻译： 公开了一种用于处理大面积，在制程中的电路板层的系统。 电路板层薄而脆弱，并且对于某些加工步骤需要刚性支撑。 该系统包括用于围绕和支撑过程电路板层的外围框架固定装置，以及用于将工艺中电路板层安装在周边框架固定装置中的装载卡盘。 外围框架固定装置包括具有中央开口以暴露电路板层的底板，具有相应中心开口以露出电路板层的相对表面的顶部框架，以及压缩装置，如螺钉，螺栓或 用于将z轴压缩力施加到底板，顶部框架以及它们之间的面板层。 可选地，固定装置可以包括用于对准底板，面板层和顶部框架的对准销或基准，以及用于机器人臂来抓握和传送外围框架固定装置的机器人界面。 该系统还包括用于将工艺中电路板层安装在外围框架固定装置中的装载卡盘。 装载卡盘包括用于接收外围框架固定装置的底板的外围边缘。 这提供了工艺电路板层，外围框架固定装置的底板和真空工作台的共面性。 真空工作台位于由装载卡盘周边边缘和外围框架固定装置的外围框架所限定的区域内，与它们共面。 真空工作台包括可滑动的支承表面，具有用于拉伸真空以将面板保持在适当位置的真空孔，以及用于移动可滑动的支承表面以将x-y轴张力施加到支承表面上的面板的致动器。

公开(公告)号：US06965502B2

公开(公告)日：2005-11-15

申请号：US10103980

申请日：2002-03-22

申请人： Thomas P. Duffy ,  Ryan Goodfellow ,  Malay Trivedi ,  Kevin Mori ,  Benjamim Tang

发明人： Thomas P. Duffy ,  Ryan Goodfellow ,  Malay Trivedi ,  Kevin Mori ,  Benjamim Tang

IPC分类号： G06F1/30 ,  H02H9/00

CPC分类号： G06F1/305

摘要： The present invention provides a power regulation system and method with high speed signal settling capabilities for providing rapid active transient response to a microelectronic device. An active transient response system includes a power supply configured to receive external and/or internal signals indicating the occurrence of transient load conditions and to respond to the transient load conditions based on one or more of these signals. The system may further include a transient suppressor configured for early detection of transients, assisting in transient suppression, and early signaling of transient activity to the power supply.The system provides rapid recovery to steady state operation from the active transient response mode by using a digital compensator to quickly modifying the duty cycle and provide a voltage offset proportional to the transient microprocessor load step. Recovery is further improved by current rephasing techniques.

摘要翻译： 本发明提供了一种具有高速信号稳定能力的功率调节系统和方法，用于向微电子器件提供快速的主动瞬态响应。 有源瞬态响应系统包括被配置为接收指示瞬态负载状况的发生的外部和/或内部信号的电源，并且基于这些信号中的一个或多个来响应瞬态负载条件。 该系统还可以包括被配置为用于早期检测瞬态，辅助瞬态抑制以及对电源的瞬时活动的早期信号的瞬态抑制器。 该系统通过使用数字补偿器快速修改占空比并提供与瞬态微处理器负载阶跃成比例的电压偏移，从主动瞬态响应模式快速恢复到稳态运行。 通过目前的重塑技术进一步改善了恢复。

公开(公告)号：US5599747A

公开(公告)日：1997-02-04

申请号：US495248

申请日：1995-06-27

申请人： Ashwinkumar C. Bhatt ,  Thomas P. Duffy ,  David E. Houser ,  Gerald W. Jones ,  Jeffrey McKeveny ,  Kenneth L. Potter

发明人： Ashwinkumar C. Bhatt ,  Thomas P. Duffy ,  David E. Houser ,  Gerald W. Jones ,  Jeffrey McKeveny ,  Kenneth L. Potter

IPC分类号： H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02 ,  H01L21/60

CPC分类号： H05K1/021 ,  H01L23/145 ,  H01L23/3677 ,  H01L23/49822 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/182 ,  H05K2201/09127 ,  H05K2201/09981 ,  H05K2203/049 ,  H05K3/0061 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and partially routing this member to define a temporary support portion therein. Metallization and circuitization may then occur, following which the temporary support portion is removed. This temporary support thus assures effective support for the photoresist used as part of the circuitization process. Thus, the photoresist is capable of being applied in sheetlike form for spanning the relatively small openings of the dielectric without sagging, bowing, etc., which may adversely impact subsequent processing steps.

摘要翻译： 制造可用作芯片载体结构的电路化衬底的方法。 该方法包括提供电介质构件并部分地布置该构件以在其中限定临时支撑部分的步骤。 然后可以发生金属化和电路化，随后移除临时支撑部分。 因此，这种临时支撑物确保了作为电路化过程的一部分使用的光致抗蚀剂的有效支撑。 因此，光致抗蚀剂能够以片状形式施加以跨越电介质的相对小的开口而不会下垂，弯曲等，这可能不利地影响随后的处理步骤。