摘要:
A wafer level molding structure and a manufacturing method thereof are provided. A molding structure includes a first chip and a second chip and an adhesive layer there between. The first chip includes a first back side, a first front side and a plurality of lateral sides, in which a plurality of first front side bumps are disposed on the first front side. The second chip includes a second back side and a second front side, and a plurality of second back side bumps and second front side bumps are respectively disposed on the second back side and the second front side. A plurality of through-hole vias is disposed in the second chip, and electrically connected the second back side bumps to the second front side bumps. Adhesive materials covering the lateral sides of the first chip, and electrically connect the second back side bumps with the first front side bumps. The adhesive materials include a plurality of conductive particles and/or a plurality of non-conductive particles.
摘要:
A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.
摘要:
A sealed joint structure of device includes a buffer bump layer, conductive joint portions and a sealed joint portion. The buffer bump layer disposed between a device and a substrate includes first parts and a second part surrounding the first parts. Each of the conductive joint portions includes a first electrode covering each of the first parts and a second electrode on the substrate, and each of the first electrodes is electrically connected to the second electrode. The sealed joint portion includes a joint ring located on the substrate and is jointed with the second part to form a hermetic space between the device and the substrate.
摘要:
After a fabrication process intended to miniaturize semiconductor devices, a surface area of a stack capacitor in a random access memory (RAM) is significantly reduced and capacity thereof is thus decreased, which in turn causes the capacitor not able to function properly. The present invention provides a composite lower electrode structure consisting of an exterior annular pipe and a central pillar having concave-convex surfaces to increase a surface area of the capacitor within a limited memory cell so as to enhance the capacity. To reinforce intensity of a structure of the capacitor, the exterior annular pipe has an elliptic radial cross section and a thicker thickness along a short axis direction.
摘要:
An electronic assembly comprising a first substrate, a number of bonds on the first substrate, a second substrate spaced apart from the first substrate, a number of bumps on the second substrate, each of the bumps including an insulating body and a conductive portion, the conductive portion extending from a top surface of the insulating body via at least one sidewall of the insulating body toward the second substrate, and an adhesive between the first substrate and the second substrate, the adhesive including an insulating layer and a conductive layer, the insulating layer and the conductive layer being laminated with respect to each other, wherein the insulating layer is positioned closer to the first substrate than the conductive layer.
摘要:
A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.
摘要:
A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.
摘要:
The invention provides an electronic device package structure and method of fabrication thereof. The electronic device package structure includes a chip having an active surface and a bottom surface. A dielectric layer is disposed on the active surface of the chip. At least one trench is formed through the dielectric layer. A first protection layer covers the dielectric layer and sidewalls of the trench. A second protection layer covers the first protection layer, filling the trench.
摘要:
The 3D chip-stack package comprises a component-embedded plate and a side IC. The PCB has a plurality of conductive contacts. The component-embedded plate comprises a dielectric layer; an active component embedded in the dielectric layer, one surface of each active component exposed outside the dielectric layer, the active components having a plurality of TSVs (Through Silicon Via), one ends of the TSVs exposed outside the exposed surface, the other ends of the TSVs corresponding to the conductive contacts of the PCB; and an electrical circuit on the dielectric layer and in electrical connection between the other ends of the TSVs of the active component and the corresponding conductive contacts of the PCB, respectively. The side IC has a plurality of pads. The pads are electrically connected with the exposed ends of the TSVs of the active component.
摘要:
A composite bump suitable for disposing on a substrate pad is provided. The composite bump includes a compliant body and an outer conductive layer. The coefficient of thermal expansion (CTE) of the compliant body is between 5 ppm/° C. and 200 ppm/° C. The outer conductive layer covers the compliant body and is electrically connected to the pad. The compliant body can provide a stress buffering effect for a bonding operation. Furthermore, by setting of the CTE of the compliant body within a preferable range, damages caused by thermal stress are reduced while the bonding effect is enhanced.