公开(公告)号：US20130264706A1

公开(公告)日：2013-10-10

申请号：US13908728

申请日：2013-06-03

申请人： Teak-hoon Lee ,  Won-keun Kim ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im

发明人： Teak-hoon Lee ,  Won-keun Kim ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im

IPC分类号： H01L23/498

CPC分类号： H01L23/49811 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

摘要翻译： 一种形成具有大容量且减小或最小化体积的半导体封装的方法包括：使用粘合剂层将半导体衬底附着在支撑衬底上，其中半导体衬底包括多个第一半导体芯片和切屑区域，其中 多个第一半导体芯片中的第一和第二半导体芯片通过芯片切割区域彼此分离，并且半导体衬底包括其上形成有源区域的第一表面和与第一表面相对的第二表面; 在所述多个第一半导体芯片中的第一和第二半导体芯片之间形成具有第一切口宽度的第一切割槽，使得半导体基板被分离成多个第一半导体芯片; 分别将对应于第一半导体芯片的多个第二半导体芯片附着到多个第一半导体芯片; 形成模塑层以填充第一切割槽; 以及在成形层中形成具有小于第一切口宽度的第二切口宽度的第二切割槽，以将模制层分离成覆盖多个第一半导体芯片中的一个的各个成型层和相应的一个 多个第二半导体芯片。

公开(公告)号：US20130134606A1

公开(公告)日：2013-05-30

申请号：US13587330

申请日：2012-08-16

申请人： Yun-hyeok IM ,  Won-keun KIM ,  Tae-Je CHO ,  Kyol PARK

发明人： Yun-hyeok IM ,  Won-keun KIM ,  Tae-Je CHO ,  Kyol PARK

IPC分类号： H01L23/29 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/367 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10126 ,  H01L2224/10156 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83007 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83887 ,  H01L2224/83888 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： A semiconductor package may include a substrate including a substrate pad on a top surface thereof; at least one semiconductor chip including a connection terminal electrically connected to the substrate on an active surface thereof, and mounted on the substrate; a heat release pattern formed between the substrate and the at least one semiconductor chip and configured to generate heat; and underfill resin underfilled between the substrate and the at least one semiconductor chip and comprising fillers. A semiconductor package may include a substrate including a substrate pad on a top surface thereof and a first heat release pattern configured to generate heat, and a semiconductor chip including a bonding pad formed on an active surface facing the substrate and a second heat release pattern configured to generate heat.

摘要翻译： 半导体封装可以包括在其顶表面上包括衬底焊盘的衬底; 至少一个半导体芯片，包括在其有源表面上电连接到所述衬底的连接端子，并且安装在所述衬底上; 形成在所述基板和所述至少一个半导体芯片之间并被配置为产生热量的散热图案; 以及在所述基底和所述至少一个半导体芯片之间未填充的底部填充树脂，并且包括填料。 半导体封装可以包括：衬底，其包括在其顶表面上的衬底焊盘和被配置为产生热量的第一散热图案;以及半导体芯片，其包括形成在与衬底相对的有源表面上的焊盘，以及第二散热图案， 产生热量。

公开(公告)号：US20120307445A1

公开(公告)日：2012-12-06

申请号：US13486235

申请日：2012-06-01

申请人： Yong-kwan LEE ,  Tae-sung Park ,  Won-keun Kim

发明人： Yong-kwan LEE ,  Tae-sung Park ,  Won-keun Kim

IPC分类号： H05K1/11 ,  G06F1/16 ,  H05K7/06

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  Y10T29/4916 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

摘要： A printed circuit board (PCB) includes a wire pattern that has a low processing cost and a high yield by simplifying the structure of the PCB and can increase the joining characteristics and reliability of minute bumps when a flip-chip bonding process is performed. The PCB includes a body resin layer having lower and upper surfaces, a wire pattern on or in one of the upper and lower surfaces of the body resin layer, at least one through-hole contact extending from the wire pattern through the body resin layer, and a solder resist on the upper and lower surfaces of the body resin layer, openings of the solder resist corresponding to at least one of a solder ball land and a bump land, the solder ball land and the bump land being configured to couple the PCB to a semiconductor chip.

摘要翻译： 印刷电路板（PCB）包括通过简化PCB的结构而具有低处理成本和高产量的导线图案，并且当进行倒装芯片接合处理时可以增加微小凸块的接合特性和可靠性。 PCB包括具有下表面和上表面的主体树脂层，在主体树脂层的上表面和下表面之一上或之一上的线图形，至少一个从线图形延伸通过主体树脂层的通孔接触， 以及在主体树脂层的上表面和下表面上的阻焊剂，焊料保护层的开口对应于焊球焊盘和凸块焊盘中的至少一个，焊球焊盘和焊盘焊盘被配置为将PCB 到半导体芯片。

公开(公告)号：US08241968B2

公开(公告)日：2012-08-14

申请号：US12938534

申请日：2010-11-03

申请人： Yong-kwan Lee ,  Tae-sung Park ,  Won-keun Kim

发明人： Yong-kwan Lee ,  Tae-sung Park ,  Won-keun Kim

IPC分类号： H01L21/00 ,  H01K3/00

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  Y10T29/4916 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

摘要： A printed circuit board (PCB) includes a wire pattern that has a low processing cost and a high yield by simplifying the structure of the PCB and can increase the joining characteristics and reliability of minute bumps when a flip-chip bonding process is performed. The PCB includes a body resin layer having lower and upper surfaces, a wire pattern on or in one of the upper and lower surfaces of the body resin layer, at least one through-hole contact extending from the wire pattern through the body resin layer, and a solder resist on the upper and lower surfaces of the body resin layer, openings of the solder resist corresponding to at least one of a solder ball land and a bump land, the solder ball land and the bump land being configured to couple the PCB to a semiconductor chip. If the solder ball land is on the one-layer wire pattern, the bump land is on the through-hole contact, and if the bump land is on the wire pattern, the solder ball land is on the through-hole contact.

摘要翻译： 印刷电路板（PCB）包括通过简化PCB的结构而具有低处理成本和高产量的导线图案，并且当进行倒装芯片接合处理时可以增加微小凸块的接合特性和可靠性。 PCB包括具有下表面和上表面的主体树脂层，在主体树脂层的上表面和下表面之一上或之一上的线图形，至少一个从线图形延伸通过主体树脂层的通孔接触， 以及在主体树脂层的上表面和下表面上的阻焊剂，焊料防护层的开口对应于焊球焊盘和凸块焊盘中的至少一个，焊球焊盘和焊盘焊盘被配置为将PCB 到半导体芯片。 如果焊锡球焊盘位于单层导线图案上，则凸起焊盘在通孔接触处，如果焊盘焊盘位于焊丝图案上，则焊球焊盘位于通孔接触处。

公开(公告)号：US20110104475A1

公开(公告)日：2011-05-05

申请号：US12914582

申请日：2010-10-28

申请人： Soon Hyung Kwon ,  Won Keun Kim ,  Jeong In Han ,  Chul Jong Han

发明人： Soon Hyung Kwon ,  Won Keun Kim ,  Jeong In Han ,  Chul Jong Han

IPC分类号： B32B5/16 ,  B32B9/04 ,  B32B27/00 ,  B32B17/06

CPC分类号： B32B5/16 ,  Y10T428/25 ,  Y10T428/31504 ,  Y10T428/3154 ,  Y10T428/31855

摘要： A substrate unit for an electronic paper is provided. The substrate unit for the electronic paper includes a substrate; an electrode formed on the substrate; and a hydrophobic polymer layer formed on at least one of an outer side of the substrate and the electrode.

摘要翻译： 提供了一种用于电子纸的基板单元。 电子纸的基板单元包括基板; 形成在基板上的电极; 以及形成在所述基板的外侧和所述电极中的至少一个上的疏水性聚合物层。

公开(公告)号：US20070052089A1

公开(公告)日：2007-03-08

申请号：US11366456

申请日：2006-03-03

申请人： Won-Keun Kim ,  Tae-Sung Park

发明人： Won-Keun Kim ,  Tae-Sung Park

IPC分类号： H01L23/34

CPC分类号： H01L24/83 ,  C09J7/10 ,  C09J2205/102 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/274 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/2939 ,  H01L2224/29499 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/325 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06593 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed herein are an adhesive film having a multiple filler distribution and a method of manufacturing the same, and a chip stack package having the adhesive film and a method of manufacturing the same. The adhesive film may have an upper film layer with a high concentration of fillers with a small particle size, and a lower film layer with a low concentration of fillers of a large particle size. The adhesive film having a multiple filler distribution may be manufactured using a lamination method or a consecutive coating method. The adhesive film may include two film layers having identical chemical properties while having different physical properties.

摘要翻译： 本文公开了具有多重填料分布的粘合剂膜及其制造方法，以及具有粘合剂膜的芯片堆叠封装及其制造方法。 粘合剂膜可以具有具有小颗粒尺寸的高浓度填料的上部膜层和具有较小粒径的低浓度填料的下部膜层。 具有多重填料分布的粘合膜可以使用层压法或连续涂布法制造。 粘合剂膜可以包括具有相同化学性质的两个膜层，同时具有不同的物理性质。

公开(公告)号：US20150130078A1

公开(公告)日：2015-05-14

申请号：US14499591

申请日：2014-09-29

申请人： Ji-seok Hong ,  Won-keun Kim ,  Tae-je Cho ,  Jung-hwan Kim

发明人： Ji-seok Hong ,  Won-keun Kim ,  Tae-je Cho ,  Jung-hwan Kim

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/34 ,  H01L23/48

CPC分类号： H01L23/34 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/367 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package of a POP structure includes first and second semiconductor packages, the second directly mounted on the first and containing a plurality of semiconductor chips. Chips in the second package are electrically connected via a through-electrode and the first and second packages are connected through a connection member disposed on the top surface of the first package.

摘要翻译： POP结构的半导体封装包括第一和第二半导体封装，第二半导体封装直接安装在第一和第二半导体封装上，并且包含多个半导体芯片。 第二封装中的芯片经由贯通电极电连接，第一和第二封装通过布置在第一封装的顶表面上的连接构件连接。

公开(公告)号：US20140134798A1

公开(公告)日：2014-05-15

申请号：US14158131

申请日：2014-01-17

申请人： Won-keun KIM ,  Hyun-jung SONG ,  Eun-young CHOI ,  Hye-young JANG

发明人： Won-keun KIM ,  Hyun-jung SONG ,  Eun-young CHOI ,  Hye-young JANG

IPC分类号： H01L25/00 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A semiconductor package including an internal package including at least one semiconductor chip sealed with an internal seal, an external substrate on which the internal package is mounted, and an external seal sealing the internal package is provided. Also provided is a method of manufacturing the semiconductor package including forming an internal package including at least one semiconductor chip sealed with an internal seal, mounting the internal package on an external substrate, and sealing the internal package with an external seal. The internal seal and the external seal have different Young's moduli, for example, a Young's modulus of the internal seal is smaller than a Young's modulus of the external seal. Accordingly, the semiconductor package is less susceptible to warpage and can be handled with relative ease in subsequent semiconductor package processes.

摘要翻译： 一种半导体封装，包括：内部封装，其包括至少一个用内部密封件密封的半导体芯片;外部基板，其上安装有内部封装;以及外部密封件封装内部封装。 还提供了一种制造半导体封装的方法，包括形成包括至少一个用内部密封件密封的半导体芯片的内部封装，将内部封装安装在外部基板上，并用外部密封件密封内部封装。 内部密封件和外部密封件具有不同的杨氏模量，例如，内部密封件的杨氏模量小于外部密封件的杨氏模量。 因此，半导体封装不易翘曲，并且可以在随后的半导体封装工艺中相对容易地处理。

公开(公告)号：US08637969B2

公开(公告)日：2014-01-28

申请号：US13908728

申请日：2013-06-03

申请人： Teak-hoon Lee ,  Won-keun Kim ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im

发明人： Teak-hoon Lee ,  Won-keun Kim ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/49811 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

摘要翻译： 一种形成具有大容量和减小或最小化体积的半导体封装的方法包括：使用粘合剂层将半导体衬底附着在支撑衬底上，其中半导体衬底包括多个第一半导体芯片和切屑区域，其中 多个第一半导体芯片中的第一和第二半导体芯片通过芯片切割区域彼此分离，并且半导体衬底包括其上形成有源区域的第一表面和与第一表面相对的第二表面; 在所述多个第一半导体芯片中的第一和第二半导体芯片之间形成具有第一切口宽度的第一切割槽，使得半导体基板被分离成多个第一半导体芯片; 分别将对应于第一半导体芯片的多个第二半导体芯片附着到多个第一半导体芯片; 形成模塑层以填充第一切割槽; 以及在成形层中形成具有小于第一切口宽度的第二切口宽度的第二切割槽，以将模制层分离成覆盖多个第一半导体芯片中的一个的各个成型层和相应的一个 多个第二半导体芯片。

公开(公告)号：US20130082399A1

公开(公告)日：2013-04-04

申请号：US13565111

申请日：2012-08-02

申请人： Won-keun Kim ,  Hyun-jung Song ,  Eun-young Choi ,  Hye-young Jang

发明人： Won-keun Kim ,  Hyun-jung Song ,  Eun-young Choi ,  Hye-young Jang

IPC分类号： H01L23/522

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A semiconductor package including an internal package including at least one semiconductor chip sealed with an internal seal, an external substrate on which the internal package is mounted, and an external seal sealing the internal package is provided. Also provided is a method of manufacturing the semiconductor package including forming an internal package including at least one semiconductor chip sealed with an internal seal, mounting the internal package on an external substrate, and sealing the internal package with an external seal. The internal seal and the external seal have different Young's moduli, for example, a Young's modulus of the internal seal is smaller than a Young's modulus of the external seal. Accordingly, the semiconductor package is less susceptible to warpage and can be handled with relative ease in subsequent semiconductor package processes.

摘要翻译： 一种半导体封装，包括：内部封装，其包括至少一个用内部密封件密封的半导体芯片;外部基板，其上安装有内部封装;以及外部密封件封装内部封装。 还提供了一种制造半导体封装的方法，包括形成包括至少一个用内部密封件密封的半导体芯片的内部封装，将内部封装安装在外部基板上，并用外部密封件密封内部封装。 内部密封件和外部密封件具有不同的杨氏模量，例如，内部密封件的杨氏模量小于外部密封件的杨氏模量。 因此，半导体封装不易翘曲，并且可以在随后的半导体封装工艺中相对容易地处理。