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公开(公告)号：US5599747A
公开(公告)日：1997-02-04
申请号：US495248
申请日：1995-06-27
申请人： Ashwinkumar C. Bhatt , Thomas P. Duffy , David E. Houser , Gerald W. Jones , Jeffrey McKeveny , Kenneth L. Potter
发明人： Ashwinkumar C. Bhatt , Thomas P. Duffy , David E. Houser , Gerald W. Jones , Jeffrey McKeveny , Kenneth L. Potter
IPC分类号： H01L23/12 , H01L23/14 , H01L23/367 , H01L23/498 , H05K1/02 , H05K1/03 , H05K1/18 , H05K3/00 , H05K7/02 , H01L21/60
CPC分类号： H05K1/021 , H01L23/145 , H01L23/3677 , H01L23/49822 , H01L2224/45144 , H01L2224/48091 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H05K1/182 , H05K2201/09127 , H05K2201/09981 , H05K2203/049 , H05K3/0061 , Y10T29/4913 , Y10T29/49155
摘要： A method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and partially routing this member to define a temporary support portion therein. Metallization and circuitization may then occur, following which the temporary support portion is removed. This temporary support thus assures effective support for the photoresist used as part of the circuitization process. Thus, the photoresist is capable of being applied in sheetlike form for spanning the relatively small openings of the dielectric without sagging, bowing, etc., which may adversely impact subsequent processing steps.
摘要翻译： 制造可用作芯片载体结构的电路化衬底的方法。 该方法包括提供电介质构件并部分地布置该构件以在其中限定临时支撑部分的步骤。 然后可以发生金属化和电路化，随后移除临时支撑部分。 因此，这种临时支撑物确保了作为电路化过程的一部分使用的光致抗蚀剂的有效支撑。 因此，光致抗蚀剂能够以片状形式施加以跨越电介质的相对小的开口而不会下垂，弯曲等，这可能不利地影响随后的处理步骤。
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2.发明授权
公开(公告)号：US5578796A
公开(公告)日：1996-11-26
申请号：US466081
申请日：1995-06-06
CPC分类号： H05K3/184 , H01L21/4807 , H05K3/4697 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/15153 , H01L2924/1517 , H05K1/021 , H05K1/182 , H05K2201/09845 , H05K2203/063 , H05K2203/308 , H05K3/0061 , H05K3/4611 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155
摘要： According to the present invention, a method of laminating at least two substrates together and circuitizing at least one surface of the laminate is provided. Pressure is exerted against opposite surfaces of each of said two substrates. An opening extends from a circuit-receiving surface of at least one of said substrates. A plug is provided which is configured to removably fit into said opening and has a support surface thereon which is substantially coplanar with the circuit-receiving surface when said plug is positioned in the opening. The plug is inserted in the opening with the support surface substantially coplanar with the circuit-receiving surface. The substrates are laminated by application of pressure on the opposite surfaces of the substrates. The circuit-receiving surface and the support surface are covered with a sheet of dry film photoresist to seal around the opening with said plug member supporting said sheet of photoresist in the region of the opening. The dry film resist material is patterned and developed in a predetermined pattern, and the surface is circuitized with electrical circuitry. Any remaining photoresist is stripped, and said plug member is removed.
摘要翻译： 根据本发明，提供了将至少两个基板层合在一起并使层压体的至少一个表面电路化的方法。 对所述两个基板的每一个的相对表面施加压力。 开口从至少一个所述基板的电路接收表面延伸。 提供插头，其构造成可移除地装配到所述开口中并且具有其上的支撑表面，当所述插头位于开口中时，该支撑表面基本上与电路接收表面共面。 插头插入开口中，支撑表面基本上与电路接收表面共面。 通过在衬底的相对表面上施加压力来层压衬底。 电路接收表面和支撑表面被一片干膜光致抗蚀剂覆盖，以在开口的区域中用支撑所述光致抗蚀剂片的插塞构件围绕开口密封。 干膜抗蚀剂材料以预定图案被图案化和显影，并且表面被电路电路化。 剥离任何剩余的光致抗蚀剂，并且去除所述插塞构件。
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3.发明授权
公开(公告)号：US5542175A
公开(公告)日：1996-08-06
申请号：US359491
申请日：1994-12-20
CPC分类号： H05K3/184 , H01L21/4807 , H05K3/4697 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/15153 , H01L2924/1517 , H05K1/021 , H05K1/182 , H05K2201/09845 , H05K2203/063 , H05K2203/308 , H05K3/0061 , H05K3/4611 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155
摘要： According to the present invention, a method of laminating at least two substrates together and circuitizing at least one surface of the laminate is provided. Pressure is exerted against opposite surfaces of each of said two substrates. An opening extends from a circuit-receiving surface of at least one of said substrates. A plug is provided which is configured to removably fit into said opening and has a support surface thereon which is substantially coplanar with the circuit-receiving surface when said plug is positioned in the opening. The plug is inserted in the opening with the support surface substantially coplanar with the circuit-receiving surface. The substrates are laminated by application of pressure on the opposite surfaces of the substrates. The circuit-receiving surface and the support surface are covered with a sheet of dry film photoresist to seal around the opening with said plug member supporting said sheet of photoresist in the region of the opening. The dry film resist material is patterned and developed in a predetermined pattern, and the surface is circuitized with electrical circuitry. Any remaining photoresist is stripped, and said plug member is removed.
摘要翻译： 根据本发明，提供了将至少两个基板层合在一起并使层压体的至少一个表面电路化的方法。 对所述两个基板的每一个的相对表面施加压力。 开口从至少一个所述基板的电路接收表面延伸。 提供插头，其构造成可移除地装配到所述开口中并且具有其上的支撑表面，当所述插头位于开口中时，该支撑表面基本上与电路接收表面共面。 插头插入开口中，支撑表面基本上与电路接收表面共面。 通过在衬底的相对表面上施加压力来层压衬底。 电路接收表面和支撑表面被一片干膜光致抗蚀剂覆盖，以在开口的区域中用支撑所述光致抗蚀剂片的插塞构件围绕开口密封。 干膜抗蚀剂材料以预定图案被图案化和显影，并且表面被电路电路化。 剥离任何剩余的光致抗蚀剂，并且去除所述插塞构件。
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公开(公告)号：US06919514B2
公开(公告)日：2005-07-19
申请号：US10661552
申请日：2003-09-15
CPC分类号： H05K3/465 , H05K3/0032 , H05K3/045 , H05K3/107 , H05K3/184 , H05K3/388 , H05K3/4661 , H05K2203/072 , H05K2203/107 , H05K2203/1338 , Y10T29/49124
摘要： Embedded flush circuitry features are provided by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a layer of dielectric material.
摘要翻译： 通过在激光烧蚀沟槽的侧壁和底部上提供导电种子层来提供嵌入式嵌入式电路特征，其特征在于将一层导电金属镀在种子层上并沉积介电材料层。
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公开(公告)号：US5229550A
公开(公告)日：1993-07-20
申请号：US847122
申请日：1992-03-31
申请人： Perminder S. Bindra , Dennis A. Canfield , Voya Rista Markovich , Jeffrey McKeveny , Robert E. Ruane , Edwin L. Thomas
发明人： Perminder S. Bindra , Dennis A. Canfield , Voya Rista Markovich , Jeffrey McKeveny , Robert E. Ruane , Edwin L. Thomas
CPC分类号： H05K3/462 , H05K3/445 , H05K1/0272 , H05K2201/0305 , H05K2201/0373 , H05K2201/09536 , H05K2201/09563 , H05K2201/09572 , H05K2201/0959 , H05K2201/096 , H05K2203/0307 , H05K2203/054 , H05K3/0023 , H05K3/28 , H05K3/36 , H05K3/4038 , H05K3/4069 , H05K3/4076 , H05K3/423 , H05K3/428
摘要： A structure and method are disclosed for making high density circuit board. Using photosensitive or other dielectric materials over a circuitized power core, vias and lands are opened up, filled with joining metal and aligned with the next level, eliminating a major registration problem in building up a high density composite and reducing the number of steps in the manufacturing process.
摘要翻译： 公开了一种用于制造高密度电路板的结构和方法。 在电路化电源核心上使用光敏或其他电介质材料，通孔和焊盘被打开，填充有接合金属并与下一级对齐，从而消除了建立高密度复合材料的主要配准问题，并减少了 制造工艺。
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公开(公告)号：US07007378B2
公开(公告)日：2006-03-07
申请号：US10317329
申请日：2002-12-12
IPC分类号： H01R9/00
CPC分类号： H05K3/244 , Y10T29/49117 , Y10T29/49147 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917
摘要： A process for manufacturing a land grid array connector for a printed wiring board is disclosed. The process does not require electroplating precious metal overlays. Therefore, no commoning bar is required. Another benefit of the invention includes a connector design using only a flash, soft gold application in the outer surface of the connector. Physical hardness and durability are derived from a thin palladium layer lying beneath the flash gold layer.
摘要翻译： 公开了一种制造用于印刷电路板的焊盘格栅阵列连接器的方法。 该过程不需要电镀贵金属覆盖层。 因此，不需要通用条。 本发明的另一个优点包括仅在连接器的外表面中使用闪光灯，软金应用的连接器设计。 物理硬度和耐久性源自位于闪金属层下面的薄钯层。
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公开(公告)号：US06730857B2
公开(公告)日：2004-05-04
申请号：US09804921
申请日：2001-03-13
IPC分类号： H05K109
CPC分类号： H05K3/465 , H05K3/0032 , H05K3/045 , H05K3/107 , H05K3/184 , H05K3/388 , H05K3/4661 , H05K2203/072 , H05K2203/107 , H05K2203/1338 , Y10T29/49124
摘要： Embedded flush circuitry features are fabricated by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a later of dielectric material.
摘要翻译： 通过在激光烧蚀沟槽的侧壁和底部提供导电种子层来制造嵌入式嵌入式电路特征，其特征在于将一层导电金属镀在种子层上并沉积以后的介电材料。
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公开(公告)号：US5129142A
公开(公告)日：1992-07-14
申请号：US605615
申请日：1990-10-30
申请人： Perminder S. Bindra , Dennis A. Canfield , Voya R. Markovich , Jeffrey McKeveny , Robert E. Ruane , Edwin L. Thomas
发明人： Perminder S. Bindra , Dennis A. Canfield , Voya R. Markovich , Jeffrey McKeveny , Robert E. Ruane , Edwin L. Thomas
CPC分类号： H05K3/462 , H05K3/445 , H05K1/0272 , H05K2201/0305 , H05K2201/0373 , H05K2201/09536 , H05K2201/09563 , H05K2201/09572 , H05K2201/096 , H05K2203/0307 , H05K2203/054 , H05K3/0023 , H05K3/28 , H05K3/36 , H05K3/4038 , H05K3/4069 , H05K3/4076 , H05K3/423 , H05K3/428 , Y10T29/49126 , Y10T29/49165
摘要： A structure and method are disclosed for making high density circuit board. Using photosensitive or other dielectric materials over a circuitized power core, vias and lands are opened up, filled with joining metal and aligned with the next level, eliminating a major registration problem in building up a high density composite and reducing the number of steps in the manufacturing process.
摘要翻译： 公开了一种用于制造高密度电路板的结构和方法。 在电路化电源核心上使用光敏或其他电介质材料，通孔和焊盘被打开，填充有接合金属并与下一级对齐，从而消除了建立高密度复合材料的主要配准问题，并减少了 制造工艺。
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公开(公告)号：US07070909B2
公开(公告)日：2006-07-04
申请号：US10928178
申请日：2004-08-30
CPC分类号： D03D1/0082 , B32B5/26 , B32B17/04 , C03C25/42 , D03D15/0011 , H05K1/0366 , H05K3/0082 , H05K2201/0112 , H05K2201/029 , Y10S428/901 , Y10T156/10 , Y10T428/31525 , Y10T442/2008 , Y10T442/2926 , Y10T442/2951 , Y10T442/2992 , Y10T442/3976
摘要： The glass transmittance of UV light having a wavelength of 365 nanometers is reduced by compounding an oxide or salt of at least one of Fe, Cu, Cr, Ce, Mn and mixtures thereof. The fiberglass cloth can be used for providing reinforced prepregs used in producing printed circuit boards or laminated chip carrier substrates.
摘要翻译： 通过配合Fe，Cu，Cr，Ce，Mn及其混合物中的至少一种的氧化物或盐来减少波长为365纳米的UV光的玻璃透射率。 玻璃纤维布可用于制造用于制造印刷电路板或层压芯片载体基板的增强预浸料。
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公开(公告)号：US06838400B1
公开(公告)日：2005-01-04
申请号：US09046105
申请日：1998-03-23
CPC分类号： D03D1/0082 , B32B5/26 , B32B17/04 , C03C25/42 , D03D15/0011 , H05K1/0366 , H05K3/0082 , H05K2201/0112 , H05K2201/029 , Y10S428/901 , Y10T156/10 , Y10T428/31525 , Y10T442/2008 , Y10T442/2926 , Y10T442/2951 , Y10T442/2992 , Y10T442/3976
摘要： The glass transmittance of UV light having a wavelength of 365 nanometers is reduced by compounding an oxide or salt of at least one of Fe, Cu, Cr, Ce, Mn and mixtures thereof. The fiberglass cloth can be used for providing reinforced prepregs used in producing printed circuit boards or laminated chip carrier substrates.
摘要翻译： 通过配合Fe，Cu，Cr，Ce，Mn及其混合物中的至少一种的氧化物或盐来减少波长为365纳米的UV光的玻璃透射率。 玻璃纤维布可用于制造用于制造印刷电路板或层压芯片载体基板的增强预浸料。
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