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1.发明授权Method and apparatus for forming stacked die and substrate structures for increased packing density 有权用于形成堆叠的管芯和衬底结构以增加堆积密度的方法和装置公开(公告)号：US07250675B2
公开(公告)日：2007-07-31
申请号：US10908277
申请日：2005-05-05
Applicant: Benjamin V. Fasano , Brian R. Sundlof
Inventor： Benjamin V. Fasano , Brian R. Sundlof
IPC: H01L23/34
CPC classification number: H01L25/0657 , H01L2224/16 , H01L2224/73253 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/16152 , H01L2924/1627 , H01L2924/3025 , H01L2224/0401
Abstract: A stacked semiconductor apparatus has at least one die attached to a first side of a carrier substrate. A first circuitized substrate is attached to the first side of the carrier substrate and overlying the at least one die in a manner such that the first circuitized substrate serves as an electrical interconnection device and a heat spreading lid. The first circuitized substrate is further configured so as to facilitate cooling of the at least one die by at least a cross flow of a cooling medium therethrough.
Abstract translation: 叠层半导体装置具有至少一个附着在载体基板的第一侧的管芯。 第一电路化基板被附接到载体基板的第一侧并且以使得第一电路化基板用作电互连装置和散热盖的方式覆盖至少一个管芯。 第一电路化基板被进一步构造成便于通过至少一个冷却介质的横流而使至少一个管芯冷却。
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2.发明授权Method and apparatus for forming stacked die and substrate structures for increased packing density 有权用于形成堆叠的管芯和衬底结构以增加堆积密度的方法和装置公开(公告)号：US07611923B2
公开(公告)日：2009-11-03
申请号：US11740962
申请日：2007-04-27
Applicant: Benjamin V. Fasano , Brian R. Sundlof
Inventor： Benjamin V. Fasano , Brian R. Sundlof
IPC: H01L21/44
CPC classification number: H01L25/0657 , H01L2224/16 , H01L2224/73253 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/16152 , H01L2924/1627 , H01L2924/3025 , H01L2224/0401
Abstract: A stacked semiconductor apparatus has at least one die attached to a first side of a carrier substrate. A first circuitized substrate is attached to the first side of the carrier substrate and overlying the at least one die in a manner such that the first circuitized substrate serves as an electrical interconnection device and a heat spreading lid. The first circuitized substrate is further configured so as to facilitate cooling of the at least one die by at least a cross flow of a cooling medium therethrough.
Abstract translation: 叠层半导体装置具有至少一个附着在载体基板的第一侧的管芯。 第一电路化基板被附接到载体基板的第一侧并且以使得第一电路化基板用作电互连装置和散热盖的方式覆盖至少一个管芯。 第一电路化基板被进一步构造成便于通过至少一个冷却介质的横流而使至少一个管芯冷却。
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公开(公告)号：US08493746B2
公开(公告)日：2013-07-23
申请号：US12704592
申请日：2010-02-12
Applicant: Charles L. Arvin , Alexandre Blander , Peter J. Brofman , Donald W. Henderson , Gareth G. Hougham , Hsichang Liu , Eric D. Perfecto , Srinivasa S. N. Reddy , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof , Julien Sylvestre , Renee L. Weisman
Inventor： Charles L. Arvin , Alexandre Blander , Peter J. Brofman , Donald W. Henderson , Gareth G. Hougham , Hsichang Liu , Eric D. Perfecto , Srinivasa S. N. Reddy , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof , Julien Sylvestre , Renee L. Weisman
CPC classification number: H01B1/02 , B23K35/0244 , B23K35/262 , B23K35/36 , B23K35/3602 , B82Y30/00 , C22C13/00 , H01B13/00 , H01L23/49866 , H01L2924/0002 , H05K3/3436 , H05K3/3463 , H05K2201/0209 , H05K2201/0257 , Y10T29/49117 , H01L2924/00
Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.
Abstract translation: 在本发明的一个实施方案中，将尺寸为1nm至1000nm的惰性纳米尺寸颗粒加入到焊球中。 惰性纳米尺寸颗粒可以包括金属氧化物，金属氮化物，金属碳化物，金属硼化物等。惰性纳米尺寸颗粒可以是单一化合物，或者可以是具有不同材料的涂层的金属材料。 在本发明的另一个实施方案中，将少量与锡形成稳定的高熔点金属间化合物的元素金属添加到焊料球中。 添加的至少一种元素金属与锡形成金属间化合物的沉淀物，其作为细颗粒分散在焊料中。
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4.发明申请SELF ORIENTING MICRO PLATES OF THERMALLY CONDUCTING MATERIAL AS COMPONENT IN THERMAL PASTE OR ADHESIVE 有权自热导热材料作为热熔胶或粘合剂中的组分的微板公开(公告)号：US20120211159A1
公开(公告)日：2012-08-23
申请号：US11758457
申请日：2007-06-05
Applicant: Gareth Hougham , Paul A. Lauro , Brian R. Sundlof , Jeffrey D. Gelorme
Inventor： Gareth Hougham , Paul A. Lauro , Brian R. Sundlof , Jeffrey D. Gelorme
CPC classification number: H01L23/3733 , B82Y30/00 , H01L23/373 , H01L23/3736 , H01L23/40 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , Y10S977/788 , Y10T156/10 , Y10T428/24994 , H01L2224/0401
Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.
Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。
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5.发明申请Solder Interconnect with Non-Wettable Sidewall Pillars and Methods of Manufacture 有权焊接与不可湿润的侧壁支柱和制造方法互连公开(公告)号：US20110193218A1
公开(公告)日：2011-08-11
申请号：US12700863
申请日：2010-02-05
Applicant: Charles L. Arvin , Raschid J. Bezama , Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , David L. Questad , Wolfgang Sauter , Timothy D. Sullivan , Brian R. Sundlof
Inventor： Charles L. Arvin , Raschid J. Bezama , Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , David L. Questad , Wolfgang Sauter , Timothy D. Sullivan , Brian R. Sundlof
IPC: H01L23/498 , H01L21/768
CPC classification number: H01L24/13 , H01L23/49811 , H01L24/11 , H01L24/16 , H01L2224/0401 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/10126 , H01L2224/11334 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/119 , H01L2224/13017 , H01L2224/13018 , H01L2224/1308 , H01L2224/13083 , H01L2224/13084 , H01L2224/13101 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13565 , H01L2224/1357 , H01L2224/13687 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/3841 , H01L2924/00014 , H01L2924/01024 , H01L2924/01026 , H01L2924/01032 , H01L2924/00012 , H01L2924/00
Abstract: A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.
Abstract translation: 焊接互连结构设置有不可润湿的侧壁及其制造方法。 该方法包括在下面的表面上形成镍或镍合金支柱。 该方法还包括修改镍或镍合金柱的侧壁以防止在侧壁上的焊料润湿。
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Patent Agency Ranking
6.发明申请SELF ORIENTING MICRO PLATES OF THERMALLY CONDUCTING MATERIAL AS COMPONENT IN THERMAL PASTE OR ADHESIVE 有权自热导热材料作为热熔胶或粘合剂中的组分的微板公开(公告)号：US20080202386A1
公开(公告)日：2008-08-28
申请号：US12039309
申请日：2008-02-28
Applicant: Gareth Hougham , Paul A. Lauro , Brian R. Sundlof , Jeffrey D. Gelorme
Inventor： Gareth Hougham , Paul A. Lauro , Brian R. Sundlof , Jeffrey D. Gelorme
CPC classification number: H01L23/3733 , B82Y30/00 , H01L23/373 , H01L23/3736 , H01L23/40 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , Y10S977/788 , Y10T156/10 , Y10T428/24994 , H01L2224/0401
Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.
Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。
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公开(公告)号：US20080180927A1
公开(公告)日：2008-07-31
申请号：US11627430
申请日：2007-01-26
Applicant: Paul Coteus , Gareth Geoffrey Hougham , Brian R. Sundlof
Inventor： Paul Coteus , Gareth Geoffrey Hougham , Brian R. Sundlof
CPC classification number: H05K3/3436 , H01L23/13 , H01L23/49805 , H01L23/49811 , H01L2924/0002 , H05K3/28 , H05K3/325 , H05K3/4007 , H05K3/4015 , H05K2201/0367 , H05K2201/09745 , H05K2201/1059 , H05K2201/10719 , H05K2203/167 , Y02P70/613 , Y10T29/49126 , Y10T29/4913 , H01L2924/00
Abstract: A circuit package is provided. The circuit package includes a plurality of electrically conductive pads located on a bottom surface of the circuit package, wherein at least one pad of the plurality of bottom surface pads has a recession for receiving an electrically conductive protrusion located on a substrate to which the circuit package is to be mounted.
Abstract translation: 提供电路封装。 电路封装包括位于电路封装的底表面上的多个导电焊盘，其中多个底表面焊盘中的至少一个焊盘具有用于接收位于基板上的导电突起的凹陷，电路封装 将被安装。
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8.发明授权公开(公告)号：US09111816B2
公开(公告)日：2015-08-18
申请号：US13431609
申请日：2012-03-27
Applicant: Virendra R. Jadhav , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof
Inventor： Virendra R. Jadhav , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof
CPC classification number: H01L24/13 , H01L23/562 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05666 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11901 , H01L2224/13005 , H01L2224/13013 , H01L2224/13023 , H01L2224/1308 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13171 , H01L2224/13184 , H01L2224/13655 , H01L2224/13666 , H01L2224/13671 , H01L2224/13684 , H01L2224/16235 , H01L2224/81815 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/2064 , H01L2924/351 , H01L2924/35121 , H01L2924/37001 , H01L2924/384 , Y10T156/10 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
Abstract: A multi-layer pillar is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
Abstract translation: 提供多层支柱。 多层柱用作芯片和基板之间的互连。 支柱具有至少一个低强度，高延展性变形区域，其被配置为吸收在芯片组装和热偏移期间施加的力。
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9.发明授权Self orienting micro plates of thermally conducting material as component in thermal paste or adhesive 有权导热材料的自定向微板作为热糊或粘合剂中的组分公开(公告)号：US08604623B2
公开(公告)日：2013-12-10
申请号：US13553887
申请日：2012-07-20
Applicant: Gareth Hougham , Paul A. Lauro , Brian R. Sundlof , Jeffrey D. Gelorme
Inventor： Gareth Hougham , Paul A. Lauro , Brian R. Sundlof , Jeffrey D. Gelorme
IPC: H01L23/04
CPC classification number: H01L23/3733 , B82Y30/00 , H01L23/373 , H01L23/3736 , H01L23/40 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , Y10S977/788 , Y10T156/10 , Y10T428/24994 , H01L2224/0401
Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.
Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。
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10.发明授权Self orienting micro plates of thermally conducting material as component in thermal paste or adhesive 有权导热材料的自定向微板作为热糊或粘合剂中的组分公开(公告)号：US08268282B2
公开(公告)日：2012-09-18
申请号：US11758457
申请日：2007-06-05
Applicant: Gareth Hougham , Paul A. Lauro , Brian R. Sundlof , Jeffrey D. Gelorme
Inventor： Gareth Hougham , Paul A. Lauro , Brian R. Sundlof , Jeffrey D. Gelorme
IPC: H01B1/04
CPC classification number: H01L23/3733 , B82Y30/00 , H01L23/373 , H01L23/3736 , H01L23/40 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , Y10S977/788 , Y10T156/10 , Y10T428/24994 , H01L2224/0401
Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.
Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。
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