摘要:
A warpage preventing substrate is provided. A plurality of first and second conductive traces are respectively formed on a first surface and a second surface of a core layer of the substrate, each conductive trace having a terminal, and a plurality of first and second non-functional traces are respectively formed on the first and second surfaces of the core layer at area free of the conductive traces. The first non-functional traces are arranged in different density from the second non-functional traces in a manner that, stress generated from the first conductive traces and first non-functional traces counteracts stress generated from the second conductive traces and second non-functional traces, to thereby prevent warpage of the substrate and maintain flatness of the substrate.
摘要:
A and method for fabricating a warpage-preventive circuit board is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.
摘要:
A warpage-preventive circuit board and method for fabricating the same is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.
摘要:
A printed circuit board and a method for fabricating the same is provided. A substrate having a core layer and a plurality of pairs of bond pads thereon is prepared with at least one opening formed on the core layer between each pair of the bond pads. A solder mask layer covers the core layer and fills the openings, with recessed portions formed at positions of the solder mask layer on the openings during curing of the solder mask layer. When a small passive component is mounted on the printed circuit board, a space is formed between the bottom of the passive component and the recessed portions of the solder mask layer. An encapsulating resin can flow into the space to form an insulating barrier between the bond pads to prevent bridging between the bond pads and short circuiting of the passive component.
摘要:
A warpage-preventive circuit board and method for fabricating the same is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.
摘要:
A semiconductor package with a chip supporting member is provided, including a lead frame having a die pad and a plurality of leads, and a chip supporting member mounted on a central portion of the die pad. The chip supporting member has a first surface and an opposing second surface attached to the die pad. At least a chip is mounted on the first surface of the chip supporting member to space the chip apart from the die pad via the chip supporting member, so as to prevent the chip from being damaged by thermal stress induced by CTE (coefficient of thermal expansion) mismatch between the chip and lead frame, thereby eliminating delamination, warpage and chip cracks. Moreover, the chip supporting member interposed between the chip and die pad provides greater flexibility for mounting variously sized or shaped chips on the die pad without having to use chips corresponding to profile of the die pad.
摘要:
A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.
摘要:
A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficulty.
摘要:
A sensor semiconductor device and a method for fabricating the same are provided. At least one sensor chip is mounted and electrically connected to a lead frame. A first and a second encapsulation molding processes are sequentially performed to form a transparent encapsulant for encapsulating the sensor chip and a part of the lead frame and to form a light-impervious encapsulant for encapsulating the transparent encapsulant. The transparent encapsulant has a light-pervious portion formed at a position corresponding to and above a sensor zone of the sensor chip. The light-pervious portion is exposed from the light-impervious encapsulant. Light may penetrate the light-pervious portion, without using an additional cover board, thereby reducing manufacturing steps and costs. The above arrangement avoids prior-art problems of poor reliability caused by a porous encapsulant and poor signal reception caused by interference of ambient light entering into a conventional chip only encapsulated by a transparent encapsulant.
摘要:
A semiconductor package and a method for fabricating the same are disclosed, which includes: providing a carrier board, forming a plurality of metal bumps on the carrier board, forming a metal layer on the carrier board to encapsulate the metal bumps, having at least one semiconductor chip electrically connected to the metal layer, then forming an encapsulant on the carrier board to encapsulate the semiconductor chip, and next removing the carrier board and the metal bumps to correspondingly form a plurality of grooves on surface of the encapsulant, wherein bottom and sides of the grooves are covered with the metal layer to allow electroconductive components to be effectively positioned in the grooves and completely bonded with the metal layer.