公开(公告)号：US07554197B2

公开(公告)日：2009-06-30

申请号：US11400182

申请日：2006-04-10

申请人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee ,  Wu-Chang Tu ,  Chun-Hung Lin ,  Shih Feng Chiu

发明人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee ,  Wu-Chang Tu ,  Chun-Hung Lin ,  Shih Feng Chiu

IPC分类号： H01L23/48 ,  H01L23/28 ,  H01L23/29

CPC分类号： H01L24/10 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/13 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/9202 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.

摘要翻译： 高频IC封装主要包括衬底，凸起芯片和多个导电填料，其中衬底具有从顶表面到底表面穿透的多个凸起孔。 芯片的有源表面以分别插入到凸块孔中的方式附接到基板的顶表面。 导电填料形成在凸起孔中，以将凸块电连接到基板的电路层。 高频IC封装具有更短的电路径和更薄的封装厚度。

公开(公告)号：US20070235871A1

公开(公告)日：2007-10-11

申请号：US11400182

申请日：2006-04-10

申请人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee ,  Wu-Chang Tu ,  Chun-Hung Lin ,  Shih Chiu

发明人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee ,  Wu-Chang Tu ,  Chun-Hung Lin ,  Shih Chiu

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/13 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/9202 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.

摘要翻译： 高频IC封装主要包括衬底，凸起芯片和多个导电填料，其中衬底具有从顶表面到底表面穿透的多个凸起孔。 芯片的有源表面以分别插入到凸块孔中的方式附接到基板的顶表面。 导电填料形成在凸起孔中，以将凸块电连接到基板的电路层。 高频IC封装具有更短的电路径和更薄的封装厚度。

公开(公告)号：US20070080466A1

公开(公告)日：2007-04-12

申请号：US11326789

申请日：2006-01-05

申请人： Shih-Wen Chou ,  Chun-Hung Lin ,  Wu-Chang Tu ,  Yu-Tang Pan

发明人： Shih-Wen Chou ,  Chun-Hung Lin ,  Wu-Chang Tu ,  Yu-Tang Pan

IPC分类号： H01L23/52

CPC分类号： H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85186 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A universal chip package structure including a carrier, a chip, a plurality of bonding wires, and a molding compound is provided. The carrier has a plurality of through holes, a carrying surface, and a back surface corresponding to the carrying surface. The back surface has a plurality of contacts around the through holes. The chip with an active surface and a plurality of bonding pads on the active surface is disposed on the carrying surface. The active surface is attached to the carrying surface and the through holes expose the bonding pads. The bonding wires go through the through holes to electrically connect with the bonding pads and the contacts. In addition, the shape and size of the molding compound can be adjusted for covering the chip, the contacts, and the bonding wires.

摘要翻译： 提供了包括载体，芯片，多个接合线和模塑料的通用芯片封装结构。 载体具有多个通孔，承载表面和对应于承载表面的后表面。 后表面具有围绕通孔的多个触点。 具有活性表面的芯片和有源表面上的多个接合焊盘设置在承载表面上。 活性表面附着在承载表面上，通孔露出接合垫。 接合线穿过通孔，以与接合焊盘和触点电连接。 此外，可以调整模塑料的形状和尺寸以覆盖芯片，触点和接合线。

公开(公告)号：US20070228581A1

公开(公告)日：2007-10-04

申请号：US11761299

申请日：2007-06-11

申请人： Shih-Wen Chou ,  Chun-Hung Lin ,  Wu-Chang Tu ,  Yu-Tang Pan

发明人： Shih-Wen Chou ,  Chun-Hung Lin ,  Wu-Chang Tu ,  Yu-Tang Pan

IPC分类号： H01L23/52

CPC分类号： H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85186 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A universal chip package structure including a carrier, a chip, a plurality of bonding wires, and a molding compound is provided. The carrier has a plurality of through holes, a carrying surface, and a back surface corresponding to the carrying surface. The back surface has a plurality of contacts around the through holes. The chip with an active surface and a plurality of bonding pads on the active surface is disposed on the carrying surface. The active surface is attached to the carrying surface and the through holes expose the bonding pads. The bonding wires go through the through holes to electrically connect with the bonding pads and the contacts. In addition, the shape and size of the molding compound can be adjusted for covering the chip, the contacts, and the bonding wires.

摘要翻译： 提供了包括载体，芯片，多个接合线和模塑料的通用芯片封装结构。 载体具有多个通孔，承载表面和对应于承载表面的后表面。 后表面具有围绕通孔的多个触点。 具有活性表面的芯片和有源表面上的多个接合焊盘设置在承载表面上。 活性表面附着在承载表面上，通孔露出接合垫。 接合线穿过通孔，以与接合焊盘和触点电连接。 此外，可以调整模塑料的形状和尺寸以覆盖芯片，触点和接合线。

公开(公告)号：US09502360B2

公开(公告)日：2016-11-22

申请号：US13348449

申请日：2012-01-11

申请人： Chun-Hung Lin ,  Yu-Feng Chen ,  Han-Ping Pu ,  Hung-Jui Kuo

发明人： Chun-Hung Lin ,  Yu-Feng Chen ,  Han-Ping Pu ,  Hung-Jui Kuo

IPC分类号： H01L23/52 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC分类号： H01L23/562 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00

摘要： A stress compensation for use in packaging, and a method of forming, is provided. The stress compensation layer is placed on an opposing side of a substrate from an integrated circuit die. The stress compensation layer is designed to counteract at least some of the stress exerted structures on the die side of the substrate, such as stresses exerted by a molding compound that at least partially encapsulates the first integrated circuit die. A package may also be electrically coupled to the substrate.

摘要翻译： 提供了用于包装的应力补偿，以及形成方法。 应力补偿层从集成电路管芯放置在衬底的相对侧上。 应力补偿层被设计成抵抗基板的模具侧上的应力施加结构中的至少一些，例如由至少部分地封装第一集成电路管芯的模制化合物施加的应力。 封装还可以电耦合到衬底。

公开(公告)号：US09418947B2

公开(公告)日：2016-08-16

申请号：US13406031

申请日：2012-02-27

申请人： Yu-Feng Chen ,  Chun-Hung Lin ,  Han-Ping Pu ,  Ming-Da Cheng ,  Kai-Chiang Wu

发明人： Yu-Feng Chen ,  Chun-Hung Lin ,  Han-Ping Pu ,  Ming-Da Cheng ,  Kai-Chiang Wu

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03334 ,  H01L2224/0384 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05075 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1184 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13078 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2224/05552

摘要： The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

摘要翻译： 所描述的形成用于封装封装的连接器的机构的实施例使得具有更细间距的较小连接器能够实现更小的封装尺寸和附加的连接。 一个封装上的导电元件部分地嵌入封装的模制化合物中，以与另一封装上的触点或金属焊盘结合。 通过嵌入导电元件，可以使导电元件更小，并且在导电元件和模塑料之间存在间隙。 可以通过将连接器的最大宽度添加空间余量来确定连接器的间距。 另一个封装上的各种类型的触点可以结合到导电元件上。

公开(公告)号：US08510564B2

公开(公告)日：2013-08-13

申请号：US12852209

申请日：2010-08-06

申请人： David J. Nicholson ,  David Lewis Fisher ,  Michael D. Ritche ,  Chun-Hung Lin ,  Christopher B. Dove ,  Kavitha Radhakrishnan

发明人： David J. Nicholson ,  David Lewis Fisher ,  Michael D. Ritche ,  Chun-Hung Lin ,  Christopher B. Dove ,  Kavitha Radhakrishnan

IPC分类号： H04L9/32

CPC分类号： H04L63/0815 ,  H04L63/0876 ,  H04L63/126

摘要： Embodiments are directed to establishing the integrity of a portion of data on at least one level of a plurality of network stack levels and automatically continuing an established federation relationship between at least two federation computer systems. In an embodiment, a first federation computer system receives a digital signature corresponding to a computer system signed by a digital signature which includes the computer system's identity and other federation relationship information configured to establish a trusted federation relationship between a first federation computer system and a second federation computer system. The first federation computer system attempts to validate the received digital signature at a first level of a network stack and determines that the validation at the first network stack layer was unsuccessful. The first federation computer system then validates the received digital signature at a second, different level of the network stack.

摘要翻译： 实施例涉及在多个网络堆栈级别的至少一个级别上建立数据的一部分的完整性，并且自动地在至少两个联合计算机系统之间继续建立的联合关系。 在一个实施例中，第一联合计算机系统接收与由数字签名签名的计算机系统相对应的数字签名，数字签名包括计算机系统的身份和其他联合关系信息，其被配置为在第一联合计算机系统和第二联合计算机系统之间建立信任的联合关系 联合计算机系统。 第一联合计算机系统尝试在网络堆栈的第一级验证接收到的数字签名，并确定第一网络堆栈层的验证不成功。 第一联合计算机系统然后在网络堆栈的第二个不同级别验证所接收的数字签名。

公开(公告)号：US20130048248A1

公开(公告)日：2013-02-28

申请号：US13218424

申请日：2011-08-25

申请人： Chun-Hung Lin ,  Han-Lin Chen ,  Chang-Yin Chen

发明人： Chun-Hung Lin ,  Han-Lin Chen ,  Chang-Yin Chen

IPC分类号： F28D15/04 ,  B21D53/02

CPC分类号： B21C37/154 ,  B21C37/16 ,  F28D15/0233 ,  F28D15/046 ,  Y10T29/49353

摘要： A heat pipe includes a step pipe, a mesh, and a supporting component. The step pipe has an evaporating section and two condensing sections. The condensing sections are on the two ends of the step pipe, respectively. The evaporating section lies between the two condensing sections. The inner spaces of the two condensing sections and the evaporating section are interconnected. The peripheral dimension of the evaporating section is larger than the peripheral dimension of each of the condensing sections. The mesh is contained in the step pipe and located inside the evaporating section. The supporting component is contained in the step pipe and wrapped in the mesh. The combination of these structures increases air's flow rate inside the heat pipe and improves the heat pipe's heat conduction efficiency.

摘要翻译： 热管包括台阶管，网和支撑构件。 步进管具有蒸发段和两个冷凝段。 冷凝段分别位于台阶管的两端。 蒸发部分位于两个冷凝部分之间。 两个冷凝部分和蒸发部分的内部空间相互连接。 蒸发部分的周边尺寸大于每个冷凝部分的周边尺寸。 网状物包含在台阶管中，位于蒸发段内。 支撑部件包含在台阶管中并包裹在网中。 这些结构的组合增加了热管内空气的流量，提高了热管的热传导效率。

公开(公告)号：US20120288981A1

公开(公告)日：2012-11-15

申请号：US13549814

申请日：2012-07-16

申请人： Sheng Yung Liu ,  Chin-Tien Yang ,  Chun-Hung Lin

发明人： Sheng Yung Liu ,  Chin-Tien Yang ,  Chun-Hung Lin

IPC分类号： H01L31/18

CPC分类号： H01L31/022433 ,  H01L31/02168 ,  Y02E10/50 ,  Y02E10/52

摘要： A method of manufacturing a solar cell includes the steps of: providing a substrate having a front side, a back side and a doped region; forming a conductor layer on the front side; firing the conductor layer at a temperature such that the conductor layer is formed with a first portion embedded into the doped region and a second portion other than the first portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the conductor layer so that the second portion of the conductor layer is disposed in the ARC layer; and removing the ARC layer on the conductor layer so that the conductor layer has an exposed surface exposed out of the ARC layer, wherein the exposed surface of the conductor layer is substantially flush with a first exposed surface of the ARC layer.

摘要翻译： 一种制造太阳能电池的方法包括以下步骤：提供具有正面，背面和掺杂区域的基板; 在前侧形成导体层; 在使得导体层形成有嵌入掺杂区域的第一部分和除了第一部分之外的第二部分的温度下烧制导体层; 在前侧和第二部分形成防反射涂层（ARC）层，其中ARC层覆盖导体层，使得导体层的第二部分设置在ARC层中; 以及去除所述导体层上的所述ARC层，使得所述导体层具有暴露在所述ARC层外部的暴露表面，其中所述导体层的所述暴露表面基本上与所述ARC层的第一暴露表面齐平。

公开(公告)号：US08199314B2

公开(公告)日：2012-06-12

申请号：US13288133

申请日：2011-11-03

申请人： Jui-Chung Peng ,  Tzung-Chi Fu ,  Chin-Hsiang Lin ,  Chien-Hsun Lin ,  Chun-Hung Lin ,  Yao-Wen Guo ,  Shy-Jay Lin ,  Heng-Hsin Liu

发明人： Jui-Chung Peng ,  Tzung-Chi Fu ,  Chin-Hsiang Lin ,  Chien-Hsun Lin ,  Chun-Hung Lin ,  Yao-Wen Guo ,  Shy-Jay Lin ,  Heng-Hsin Liu

IPC分类号： G03B27/52 ,  G03B27/58 ,  G03B27/60 ,  G03B27/68 ,  G03B27/42 ,  G03B27/32

CPC分类号： G03F7/70875 ,  G03F7/70341 ,  G03F7/70783

摘要： System and method for improving immersion scanner overlay performance are described. One embodiment is a method of improving overlay performance of an photolithography immersion scanner including a wafer table having lens cooling water (“LCW”) disposed in a water channel therein, the wafer table having an input for receiving the LCW into the water channel and an output for expelling the LCW from the water channel. The method includes providing a water tank that connects to at least one of the wafer table input and the wafer table output; monitoring a pressure of water in the water tank; and maintaining the pressure of the water in the water tank at a predetermined level.

摘要翻译： 描述了用于提高浸没式扫描仪覆盖性能的系统和方法。 一个实施例是一种提高光刻浸没扫描仪的覆盖性能的方法，该扫描仪包括设置在其中的水通道中的具有透镜冷却水（“LCW”）的晶片台，晶片台具有用于将LCW接收到水通道中的输入端， 输出用于从水道排出LCW。 该方法包括：提供连接到晶片台输入和晶片台输出中的至少一个的水箱; 监测水箱内的水压; 并且将水箱中的水的压力保持在预定水平。