公开(公告)号：US06548911B2

公开(公告)日：2003-04-15

申请号：US09922254

申请日：2001-08-03

申请人： Kevin Yu ,  Chien-Ping Huang ,  Che-Jung Chang

发明人： Kevin Yu ,  Chien-Ping Huang ,  Che-Jung Chang

IPC分类号： H01L2940

CPC分类号： H01L21/565 ,  H01L23/13 ,  H01L23/544 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0652 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A substrate unit has a first surface and a corresponding second surface, and a plurality of nodes and at least a die pad are formed on the first surface of the substrate unit. A plurality of external nodes is formed on the second surface of the substrate unit, and the external nodes are electrically connected to the nodes. A multimedia chip has an active surface and a corresponding back surface, and a plurality of bonding pads are formed on the active surface of the multimedia chip. The back surface of the multimedia chip is adhered on the die pad of the substrate unit. A molding compound encapsulates the multimedia chip, the first surface of the substrate unit, and the conductive wires, and exposes the second surface of the substrate unit and the external nodes.

公开(公告)号：US06541307B2

公开(公告)日：2003-04-01

申请号：US10224109

申请日：2002-08-19

申请人： Kevin Yu ,  Chien-Ping Huang ,  Che-Jung Chang

发明人： Kevin Yu ,  Chien-Ping Huang ,  Che-Jung Chang

IPC分类号： H01L2144

CPC分类号： H01L21/565 ,  H01L23/13 ,  H01L23/544 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0652 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A substrate unit has a first surface and a corresponding second surface, and a plurality of nodes and at least a die pad are formed on the first surface of the substrate unit. A plurality of external nodes is formed on the second surface of the substrate unit, and the external nodes are electrically connected to the nodes. A multimedia chip has an active surface and a corresponding back surface, and a plurality of bonding pads are formed on the active surface of the multimedia chip. The back surface of the multimedia chip is adhered on the die pad of the substrate unit. A molding compound encapsulates the multimedia chip, the first surface of the substrate unit, and the conductive wires, and exposes the second surface of the substrate unit and the external nodes.

公开(公告)号：US08198689B2

公开(公告)日：2012-06-12

申请号：US12769041

申请日：2010-04-28

申请人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

发明人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

IPC分类号： H01L23/485

CPC分类号： H01L21/02 ,  B81B7/007 ,  B81B2207/07 ,  H01L23/52 ,  H01L29/84 ,  H01L2224/02166 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

摘要： Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.

摘要翻译： 提出具有微机电（MEMS）元件的封装结构，其包括具有多个电连接焊盘和形成在其上的MEMS元件的芯片; 设置在所述芯片上用于覆盖所述MEMS元件的盖; 设置在每个电连接焊盘上的螺柱凸块; 形成在芯片上的密封剂，其中一部分柱状凸块从密封剂暴露出来; 以及金属导电层，形成在密封剂上并连接到凸块上。 本发明的特征在于直接完成晶片上的封装工艺，以便在更短的时间内制造更薄和更便宜的封装结构。 本发明还提供如上所述的用于制造封装结构的方法。

公开(公告)号：US08079539B2

公开(公告)日：2011-12-20

申请号：US12693848

申请日：2010-01-26

申请人： Chien-Ping Huang ,  Cheng-Hsiang Kuo

发明人： Chien-Ping Huang ,  Cheng-Hsiang Kuo

IPC分类号： B65H23/18

CPC分类号： B65H59/385 ,  B65H23/1955 ,  B65H59/387 ,  B65H2553/51 ,  B65H2555/20 ,  B65H2557/264

摘要： A built-in module for an inverter and having tension control with integrated tension and velocity closed loops, where required tension feedbacks can be obtained by internal calculations of the inverter or feedback signals of a tension sensor. The tension control module is applied to provide a tension control for a winding mechanism which is operated by driving at least one motor. The tension control module firstly builds a tension control to provide a balanced tension to the winding mechanism. Afterward, the tension control module builds a velocity control to provide an accelerated or decelerated adjustment for the winding mechanism. Accordingly, the winding mechanism can stably maintain a tension-balanced operation.

摘要翻译： 内置的逆变器模块，具有集成张力和速度闭环的张力控制，可通过变频器的内部计算或张力传感器的反馈信号获得所需的张力反馈。 张力控制模块用于为通过驱动至少一个电动机而操作的卷绕机构提供张力控制。 张力控制模块首先建立张力控制以向卷绕机构提供平衡的张力。 之后，张力控制模块建立一个速度控制，为卷绕机构提供加速或减速调节。 因此，卷绕机构能够稳定地保持张力平衡动作。

公开(公告)号：US08058100B2

公开(公告)日：2011-11-15

申请号：US12788772

申请日：2010-05-27

申请人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/60

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00

摘要： A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures.

摘要翻译： 公开了一种芯片级封装结构及其制造方法。 该方法包括在载体的预定部分上形成金属垫; 在载体上安装芯片，每个芯片具有焊接到金属焊盘的多个导电凸块; 在载体上形成密封剂以封装芯片和导电凸块; 移除载体以暴露金属垫和甚至具有密封剂表面的金属垫; 在所述密封剂上形成电连接到所述金属焊盘的多个第一导电迹线; 在所述第一导电迹线上施加焊接掩模，以及在所述焊接掩模上形成多个开口以暴露所述第一导电迹线的预定部分; 在所述预定部分上形成多个导电元件; 以及切割所述密封剂以形成多个芯片级封装结构。

公开(公告)号：US08026602B2

公开(公告)日：2011-09-27

申请号：US12872164

申请日：2010-08-31

申请人： Chun-Chi Ke ,  Chien-Ping Huang

发明人： Chun-Chi Ke ,  Chien-Ping Huang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/14104 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013

摘要： A semiconductor device having conductive bumps and a fabrication method thereof are provided. The fabrication method mainly including steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with a portion of the solder pads exposed from the passivation layer; disposing a first metal layer on the solder pad and a portion of the passivation layer around the solder pad; disposing a covering layer on the first metal layer and the passivation layer, and forming an aperture in the covering layer to expose a portion of the first metal layer, wherein a center of the aperture is deviated from that of the solder pad; deposing a metal pillar on the portion of the first metal layer; and deposing a solder material on an outer surface of the metal pillar for providing a better buffering effect.

摘要翻译： 提供了具有导电凸块的半导体器件及其制造方法。 该制造方法主要包括以下步骤：提供具有焊料焊盘和形成在其上的钝化层的半导体衬底，其中一部分焊料焊盘从钝化层暴露出来; 在焊料焊盘上设置第一金属层和围绕焊盘的钝化层的一部分; 在所述第一金属层和所述钝化层上设置覆盖层，以及在所述覆盖层中形成孔以暴露所述第一金属层的一部分，其中所述孔的中心偏离所述焊盘的中心; 在所述第一金属层的所述部分上沉积金属柱; 并在金属柱的外表面上沉积焊料，以提供更好的缓冲效果。

公开(公告)号：USRE42653E1

公开(公告)日：2011-08-30

申请号：US12722009

申请日：2010-03-11

申请人： Chien-Ping Huang

发明人： Chien-Ping Huang

IPC分类号： H01L23/10 ,  H01L23/34

CPC分类号： H01L23/4334 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package with a heat dissipating structure is provided. The heat dissipating structure includes a flat portion, and a plurality of support portions formed at edge corners of the flat portion for supporting the flat portion above a chip mounted on a substrate. The support portions are mounted at predetermined area on the substrate without interfering with arrangement of the chip and bonding wires that electrically connect the chip to the substrate. The support portions are arranged to form a space embraced by adjacent supports and the flat portion, so as to allow the bonding wires to pass through the space to reach area on the substrate outside coverage of the heat dissipating structure; besides, passive components or other electronic components can be mounted on the substrate at area within or outside the coverage of the heat dissipating structure, thereby improving flexibility in component arrangement in the semiconductor package.

摘要翻译： 提供具有散热结构的半导体封装。 散热结构包括平坦部分和形成在平坦部分的边缘角部处的多个支撑部分，用于将平坦部分支撑在安装在基板上的芯片上。 支撑部分安装在基板上的预定区域上，而不干扰将芯片与基板电连接的芯片和接合线的布置。 支撑部分被布置成形成由相邻支撑件和平坦部分包围的空间，以便使接合线通过该空间以到达散热结构外部覆盖层上的基板上的区域; 此外，无源部件或其他电子部件可以在散热结构的覆盖范围内或外部的区域处安装在基板上，从而提高半导体封装中的部件布置的灵活性。

公开(公告)号：US07993967B2

公开(公告)日：2011-08-09

申请号：US12616834

申请日：2009-11-12

申请人： Yih-Jenn Jiang ,  Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Yih-Jenn Jiang ,  Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/3121 ,  H01L21/561 ,  H01L21/6835 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer. In the present invention, the distance between the semiconductor package and the external device is increased, and thermal stress caused by difference between the thermal expansion coefficients is reduced, so as to enhance the reliability of the product.

摘要翻译： 公开了半导体封装和制造方法。 制造方法包括在金属载体的一个表面上施加牺牲层，在牺牲层上施加绝缘层，以及在牺牲层和绝缘层中形成通孔以露出金属载体; 在每个通孔中形成导电金属层; 在所述绝缘层上形成图案化电路层，以电连接到所述导电金属层; 将至少一个芯片安装在所述绝缘层上并将所述芯片电连接到所述图案化电路层; 形成密封剂以封装所述芯片和所述图案化电路层; 并且去除金属载体和牺牲层以暴露绝缘层和导电金属层，以允许导电金属层从绝缘层突出。 在本发明中，半导体封装和外部器件之间的距离增加，由于热膨胀系数之差导致的热应力降低，从而提高了产品的可靠性。

公开(公告)号：US20110156227A1

公开(公告)日：2011-06-30

申请号：US12770028

申请日：2010-04-29

申请人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/495

CPC分类号： H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.

摘要翻译： 半导体封装结构包括：电介质层; 设置在电介质层上并具有芯片焊盘和迹线的金属层，每个迹线包括迹线体，延伸到管芯焊盘周边的接合焊盘和相对的迹线端; 金属柱贯穿电介质层，其一端连接到管芯焊盘并且其端部从电介质层突出; 半导体芯片，安装在芯片焊盘上，并通过接合线电连接到焊盘; 以及覆盖半导体芯片，接合线，金属层和电介质层的密封剂。 本发明的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免在现有技术中遇到的焊料桥接。

公开(公告)号：US20110129966A1

公开(公告)日：2011-06-02

申请号：US13023185

申请日：2011-02-08

申请人： Yun-Lung Tsai ,  Yu-Chieh Tsai ,  Chien-Chih Chen ,  Chien-Ping Huang

发明人： Yun-Lung Tsai ,  Yu-Chieh Tsai ,  Chien-Chih Chen ,  Chien-Ping Huang

IPC分类号： H01L21/52

CPC分类号： H01L25/18 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/15162 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K3/284 ,  H05K2201/09127 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.

摘要翻译： 提供半导体器件及其制造方法。 具有至少一个倾斜侧的开口形成在基板上。 至少一个芯片和至少一个无源部件安装在基板上。 在基板上形成具有切口角的密封剂，以封装芯片和无源部件，其中密封剂的切口角与开口的倾斜侧隔开预定距离。 进行切割处理以切割密封剂以形成具有倒角的包装。 封装被嵌入盖子中以形成半导体器件，其中位于开口的倾斜侧和密封剂的切除角之间的基底的一部分从密封剂暴露出来以形成暴露部分。 本发明还提供了一种用于半导体器件的载体。