公开(公告)号：US20130333923A1

公开(公告)日：2013-12-19

申请号：US13495545

申请日：2012-06-13

Applicant: Mihaela Balseanu ,  Stephan A. Cohen ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Son V. Nguyen ,  Mei-Yee Shek ,  Hosadurga Shobha ,  Li-Qun Xia

Inventor： Mihaela Balseanu ,  Stephan A. Cohen ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Son V. Nguyen ,  Mei-Yee Shek ,  Hosadurga Shobha ,  Li-Qun Xia

IPC: C23C16/34 ,  H05K1/02

CPC classification number: C23C16/345 ,  C23C16/56 ,  H01L21/4803 ,  H05K1/0298 ,  Y10T428/24975

Abstract: A layer of silicon nitride having a thickness from 0.5 nanometers to 2.4 nanometers is deposited on a substrate. A plasma nitridation process is carried out on the layer. These steps are repeated for a plurality of additional layers of silicon nitride, until a predetermined thickness is attained. Such steps can be used to provide a multilayer silicon nitride dielectric formed on a substrate having an upper surface of dielectric material with Cu and other conductors embedded within, and a plurality of steps. The multilayer silicon nitride dielectric has a plurality of individual layers each having a thickness from 0.5 nanometers to 2.4 nanometers, and the multilayer silicon nitride dielectric conformally covers the steps of the substrate with a conformality of at least seventy percent. A multilayer silicon nitride dielectric, and a multilevel back end of line interconnect wiring structure using same, are also provided.

Abstract translation: 将厚度为0.5纳米至2.4纳米的氮化硅层沉积在基底上。 在层上进行等离子体氮化处理。 对于多个附加氮化硅层重复这些步骤，直到达到预定厚度。 可以使用这样的步骤来提供形成在具有介电材料的上表面的衬底上的多层氮化硅电介质，其中Cu和其它导体嵌入其中并且多个步骤。 多层氮化硅电介质具有各自具有0.5纳米至2.4纳米厚度的多个单独层，多层氮化硅电介质保形地覆盖具有至少百分之七十的保形度的基底的步骤。 还提供了多层氮化硅电介质，以及使用该多层氮化硅电介质的多层后端的布线结构。

公开(公告)号：US07923386B2

公开(公告)日：2011-04-12

申请号：US12560941

申请日：2009-09-16

Applicant: Mihaela Balseanu ,  Mei-yee Shek ,  Li-Qun Xia ,  Hichem M'Saad

Inventor： Mihaela Balseanu ,  Mei-yee Shek ,  Li-Qun Xia ,  Hichem M'Saad

IPC: H01L21/31

CPC classification number: H01L21/76834 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76829 ,  H01L21/76831

Abstract: A method of forming a layer on a substrate in a chamber, wherein the substrate has at least one formed feature across its surface, is provided. The method includes exposing the substrate to a silicon-containing precursor in the presence of a plasma to deposit a layer, treating the deposited layer with a plasma, and repeating the exposing and treating until a desired thickness of the layer is obtained. The plasma may be generated from an oxygen-containing gas.

Abstract translation: 提供了一种在室中的衬底上形成层的方法，其中衬底在其表面上具有至少一个形成的特征。 该方法包括在存在等离子体的情况下将衬底暴露于含硅前体以沉积一层，用等离子体处理沉积层，并重复曝光和处理，直到获得所需层厚。 等离子体可以由含氧气体产生。

公开(公告)号：US06951826B2

公开(公告)日：2005-10-04

申请号：US10684079

申请日：2003-10-09

Applicant: Christopher Bencher ,  Joe Feng ,  Mei-Yee Shek ,  Chris Ngai ,  Judy Huang

Inventor： Christopher Bencher ,  Joe Feng ,  Mei-Yee Shek ,  Chris Ngai ,  Judy Huang

IPC: C23C16/32 ,  C30B25/10 ,  H01L21/027 ,  H01L21/04 ,  H01L21/205 ,  H01L21/314 ,  H01L21/768 ,  H01L23/532 ,  H01L21/302

CPC classification number: H01L21/0276 ,  C23C16/325 ,  C30B25/105 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/0445 ,  H01L21/314 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/931 ,  Y10S438/952 ,  H01L2924/00

Abstract: The present invention generally provides a process for depositing silicon carbide using a silane-based material with certain process parameters that is useful for forming a suitable ARC for IC applications. Under certain process parameters, a fixed thickness of the silicon carbide may be used on a variety of thicknesses of underlying layers. The thickness of the silicon carbide ARC is substantially independent of the thickness of the underlying layer for a given reflectivity, in contrast to the typical need for adjustments in the ARC thickness for each underlying layer thickness to obtain a given reflectivity. Another aspect of the invention includes a substrate having a silicon carbide anti-reflective coating, comprising a dielectric layer deposited on the substrate and a silicon carbide anti-reflective coating having a dielectric constant of less than about 7.0 and preferably about 6.0 or less.

Abstract translation: 本发明通常提供一种使用具有某些工艺参数的硅烷基材料沉积碳化硅的方法，其可用于形成用于IC应用的合适的ARC。 在某些工艺参数下，碳化硅的固定厚度可用于各种厚度的下层。 对于给定的反射率，碳化硅ARC的厚度基本上与下层的厚度无关，相比之下，为了获得给定的反射率，每个下层厚度的ARC厚度的调整的典型需要相反。 本发明的另一方面包括具有碳化硅抗反射涂层的基底，其包括沉积在基底上的电介质层和介电常数小于约7.0，优选约6.0或更小的碳化硅抗反射涂层。

公开(公告)号：US20050042889A1

公开(公告)日：2005-02-24

申请号：US10888110

申请日：2004-07-09

Applicant: Albert Lee ,  Annamalai Lakshmanan ,  Bok Kim ,  Li-Qun Xia ,  Mei-Yee Shek

Inventor： Albert Lee ,  Annamalai Lakshmanan ,  Bok Kim ,  Li-Qun Xia ,  Mei-Yee Shek

IPC: C23C16/30 ,  C23C16/40 ,  C23C16/56 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/31 ,  H01L21/336 ,  H01L21/469

CPC classification number: C23C16/30 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834

Abstract: Methods and apparatus are provided for processing a substrate with a bilayer barrier layer. In one aspect, the invention provides a method for processing a substrate including depositing a nitrogen containing barrier layer on a substrate surface and then depositing a nitrogen free barrier layer thereon. The barrier layer may be deposited over dielectric materials, conductive materials, or both. The bilayer barrier layer may also be used as an etch stop, an anti-reflective coating, or a passivation layer.

Abstract translation: 提供了用于处理具有双层阻挡层的衬底的方法和装置。 一方面，本发明提供了一种处理衬底的方法，包括在衬底表面上沉积含氮阻挡层，然后在其上沉积无氮阻挡层。 阻挡层可以沉积在电介质材料，导电材料或两者上。 双层阻挡层也可以用作蚀刻停止层，抗反射涂层或钝化层。

公开(公告)号：US06451686B1

公开(公告)日：2002-09-17

申请号：US08923501

申请日：1997-09-04

Applicant: Chris Ngai ,  Joel Glenn ,  Mei Yee Shek ,  Judy Huang

Inventor： Chris Ngai ,  Joel Glenn ,  Mei Yee Shek ,  Judy Huang

IPC: A01L214763

CPC classification number: H01L21/02131 ,  C23C16/402 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/31629 ,  H01L21/762 ,  Y10S977/891 ,  Y10S977/892

Abstract: A method and apparatus for reducing oxide traps within a silicon oxide film by incorporating a selected level of fluorine in the silicon oxide film. The method includes the steps of distributing a fluorine source to a processing chamber at a selected rate with the rate being chosen according to the desired level of fluorine to be incorporated into the film, flowing a process gas including a silicon source, an oxygen source and the fluorine source into the processing chamber, and maintaining a deposition zone within the chamber at processing conditions suitable to deposit a silicon oxide film having the selected level of fluorine incorporated into the film over a substrate disposed in the chamber. In a preferred embodiment, the selected level of fluorine incorporated into the film is between 1×1020 atoms/cm3 and 1×1021 atoms/cm3. In another preferred embodiment the silicon oxide film is deposited as a first layer of a composite layer premetal dielectric film.

Abstract translation: 一种通过在氧化硅膜中并入选定量的氟来还原氧化硅膜内的氧化物陷阱的方法和装置。 该方法包括如下步骤：以选定的速率将氟源分配到处理室，其速率根据要并入膜中的氟的期望水平来选择，流过包括硅源，氧源和 氟源进入处理室，并且在适合于将具有选定水平的氟的氧化硅膜沉积在膜中的衬底上的处理条件下保持在室内的沉积区域。 在优选的实施方案中，掺入薄膜中的所选择的氟含量为1×10 20原子/ cm 3至1×10 21原子/ cm 3。 在另一优选实施例中，氧化硅膜作为复合层前金属绝缘膜的第一层沉积。

公开(公告)号：US20120289049A1

公开(公告)日：2012-11-15

申请号：US13104314

申请日：2011-05-10

Applicant: WEIFENG YE ,  Victor Nguyen ,  Mei-Yee Shek ,  Mihaela Balseanu ,  Li-Qun Xia ,  Derek R. Witty

Inventor： WEIFENG YE ,  Victor Nguyen ,  Mei-Yee Shek ,  Mihaela Balseanu ,  Li-Qun Xia ,  Derek R. Witty

IPC: H01L21/3065 ,  H01L21/302

CPC classification number: H01L21/02074 ,  H01L21/76883

Abstract: A method for the removal of copper oxide from a copper and dielectric containing structure of a semiconductor chip is provided. The copper and dielectric containing structure may be planarized by chemical mechanical planarization (CMP) and treated by the method to remove copper oxide and CMP residues. Annealing in a hydrogen (H2) gas and ultraviolet (UV) environment removes copper oxide, and a pulsed ammonia plasma removes CMP residues.

Abstract translation: 提供了一种从铜中除去氧化铜和包含半导体芯片的结构的方法。 可以通过化学机械平面化（CMP）对包含铜和电介质的结构进行平面化，并通过除去氧化铜和CMP残留物的方法进行处理。 在氢（H2）气体和紫外线（UV）环境中退火除去氧化铜，脉冲氨等离子体去除CMP残留物。

公开(公告)号：US20120097330A1

公开(公告)日：2012-04-26

申请号：US12908617

申请日：2010-10-20

Applicant: Prahallad Iyengar ,  Sanjeev Baluja ,  Dale R. DuBois ,  Juan Carlos Rocha-Alverez ,  Thomas Nowak ,  Scott A. Hendrickson ,  Yong-Won Lee ,  Mei-Yee Shek ,  Li-Qun Xia ,  Derek R. Witty

Inventor： Prahallad Iyengar ,  Sanjeev Baluja ,  Dale R. DuBois ,  Juan Carlos Rocha-Alverez ,  Thomas Nowak ,  Scott A. Hendrickson ,  Yong-Won Lee ,  Mei-Yee Shek ,  Li-Qun Xia ,  Derek R. Witty

IPC: H01L21/465 ,  H01L21/46

CPC classification number: H01L21/02164 ,  C23C16/45565 ,  C23C16/4557 ,  C23C16/45574 ,  C23C16/463 ,  C23C16/5096 ,  H01L21/02274

Abstract: A substrate processing system includes a thermal processor or a plasma generator adjacent to a processing chamber. A first processing gas enters the thermal processor or plasma generator. The first processing gas then flows directly through a showerhead into the processing chamber. A second processing gas flows through a second flow path through the showerhead. The first and second processing gases are mixed below the showerhead and a layer of material is deposited on a substrate under the showerhead.

Abstract translation: 衬底处理系统包括与处理室相邻的热处理器或等离子体发生器。 第一处理气体进入热处理器或等离子体发生器。 然后，第一处理气体直接通过喷头流入处理室。 第二处理气体流过穿过喷头的第二流路。 第一和第二处理气体混合在喷淋头下面，并且一层材料沉积在喷头下方的基底上。

公开(公告)号：US08138104B2

公开(公告)日：2012-03-20

申请号：US11762590

申请日：2007-06-13

Applicant: Mihaela Balseanu ,  Victor Nguyen ,  Li-Qun Xia ,  Derek R. Witty ,  Hichem M'Saad ,  Mei-Yee Shek ,  Isabelita Roflox

Inventor： Mihaela Balseanu ,  Victor Nguyen ,  Li-Qun Xia ,  Derek R. Witty ,  Hichem M'Saad ,  Mei-Yee Shek ,  Isabelita Roflox

IPC: H01L21/469

CPC classification number: H01L21/3105 ,  C23C16/345 ,  C23C16/56 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/66583 ,  H01L29/7843

Abstract: Stress of a silicon nitride layer may be enhanced by deposition at higher temperatures. Employing an apparatus that allows heating of a substrate to substantially greater than 400° C. (for example a heater made from ceramic rather than aluminum), the silicon nitride film as-deposited may exhibit enhanced stress allowing for improved performance of the underlying MOS transistor device. In accordance with alternative embodiments, a deposited silicon nitride film is exposed to curing with ultraviolet (UV) radiation at an elevated temperature, thereby helping remove hydrogen from the film and increasing film stress. In accordance with still other embodiments, a silicon nitride film is formed utilizing an integrated process employing a number of deposition/curing cycles to preserve integrity of the film at the sharp corner of the underlying raised feature. Adhesion between successive layers may be promoted by inclusion of a post-UV cure plasma treatment in each cycle.

Abstract translation: 氮化硅层的应力可以通过在较高温度下沉积来增强。 使用允许将衬底加热到​​基本上大于400℃的装置（例如由陶瓷而不是铝制成的加热器），沉积的氮化硅膜可能表现出增强的应力，从而可以改善下面的MOS晶体管的性能 设备。 根据替代实施例，沉积的氮化硅膜在升高的温度下暴露于紫外线（UV）辐射固化，从而有助于从膜中除去氢并增加膜应力。 根据其他实施例，使用采用多个沉积/固化周期的整合方法形成氮化硅膜，以保持薄膜在底层凸起特征的尖角处的完整性。 可以通过在每个循环中包括UV后固化等离子体处理来促进连续层之间的粘附。

公开(公告)号：US20070202640A1

公开(公告)日：2007-08-30

申请号：US11365740

申请日：2006-02-28

Applicant: Amir Al-Bayati ,  Reza Arghavani ,  Mei-Yee Shek ,  Li-Qun Xia ,  Mihaela Balseanu ,  Bok Kim ,  Michael Cox ,  Chad Peterson ,  Hichem M'Saad

Inventor： Amir Al-Bayati ,  Reza Arghavani ,  Mei-Yee Shek ,  Li-Qun Xia ,  Mihaela Balseanu ,  Bok Kim ,  Michael Cox ,  Chad Peterson ,  Hichem M'Saad

IPC: H01L21/338

CPC classification number: H01L29/4983 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/26586 ,  H01L21/3146 ,  H01L21/31633 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

Abstract: A method of forming source and drain regions in a semiconductor transistor. The method includes the steps of forming a first sidewall spacer on sidewall surfaces of a gate electrode that is formed on an underlying substrate, where the first sidewall spacer includes amorphous carbon. The method may also include implanting the source and drain regions in the semiconductor substrate, and removing the first sidewall spacer before annealing the source and drain regions. The method may still further include forming a second sidewall spacer on the sidewall surfaces of the gate electrode, where the second sidewall spacer has a k-value less than 4. Also, a method to enhance conformality of a sidewall spacer layer. The method may include the steps of pulsing a radio-frequency power source to generate periodically a plasma, and depositing the plasma on sidewall surfaces of a gate electrode to form the sidewall spacer layer.

Abstract translation: 一种在半导体晶体管中形成源区和漏区的方法。 该方法包括以下步骤：在形成在下面的基底上的栅电极的侧壁表面上形成第一侧壁间隔物，其中第一侧壁间隔物包括无定形碳。 该方法还可以包括将源极和漏极区域注入到半导体衬底中，以及在退火源极和漏极区域之前去除第一侧壁间隔物。 该方法还可以包括在栅电极的侧壁表面上形成第二侧壁间隔物，其中第二侧壁间隔物的k值小于4.另外，增强侧壁间隔层的一致性的方法。 该方法可以包括以下步骤：脉冲射频电源周期性地产生等离子体，以及将等离子体沉积在栅电极的侧壁表面上以形成侧壁间隔层。

公开(公告)号：US20060270217A1

公开(公告)日：2006-11-30

申请号：US11398436

申请日：2006-04-05

Applicant: Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

Inventor： Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

IPC: H01L21/44

CPC classification number: H01L29/7843 ,  C23C16/345 ,  C23C16/56 ,  H01L21/28044 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/66583

Abstract: A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.