公开(公告)号：US5293301A

公开(公告)日：1994-03-08

申请号：US798736

申请日：1991-11-27

申请人： Masato Tanaka ,  Katsuya Fukase ,  Mitsuharu Shimizu ,  Toshiyuki Murakami

发明人： Masato Tanaka ,  Katsuya Fukase ,  Mitsuharu Shimizu ,  Toshiyuki Murakami

IPC分类号： H01L23/433 ,  H01L23/495 ,  H05K7/20

CPC分类号： H01L23/49558 ,  H01L23/4334 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/181

摘要： A lead frame to be used for a semiconductor device, comprising: a heat sink having a peripheral area and a central projected land on which a semiconductor chip is to be mounted. The heat sink has a relatively good heat radiating characteristic. A plurality of inner leads are provided, each having an inner end superimposed on the peripheral area of the heat sink by an insulating material. A semiconductor chip has a chip surface on which a junction pattern is arranged, and is mounted on the projected land of the heat sink by an insulating adhesive so that the chip surface faces the projected land. TAB leads are provided for electrically connecting the semiconductor chip to the inner leads, and a sealing resin hermetically seals at least the semiconductor chip.

摘要翻译： 一种用于半导体器件的引线框架，包括：具有外围区域的散热器和要安装半导体芯片的中心投影区域。 散热器具有相对较好的散热特性。 提供多个内引线，每个内引线具有通过绝缘材料重叠在散热器的周边区域上的内端。 半导体芯片具有布置有接合图案的芯片表面，并且通过绝缘粘合剂安装在散热器的投影平台上，使得芯片表面面向投影平台。 提供TAB引线用于将半导体芯片电连接到内引线，并且密封树脂至少密封半导体芯片。

公开(公告)号：US20060001179A1

公开(公告)日：2006-01-05

申请号：US11151193

申请日：2005-06-14

申请人： Katsuya Fukase ,  Shinichi Wakabayashi

发明人： Katsuya Fukase ,  Shinichi Wakabayashi

IPC分类号： H01L21/48 ,  H01L23/52

CPC分类号： H01L23/147 ,  H01L21/6835 ,  H01L23/14 ,  H01L23/3677 ,  H01L23/492 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/0401

摘要： An interposer to be interposed between a semiconductor chip to be mounted thereon and a packaging board has an interposer portion made of a semiconductor and an interposer portion provided around the foregoing interposer portion integrally therewith. On both surfaces of the interposer portions, wiring patterns are formed via insulating layers. The wiring patterns are electrically connected via through holes formed at required positions in the interposer portions. The outer interposer portion is made of an insulator or a metal body. Further, external connection terminals are bonded to one surface of the interposer.

公开(公告)号：US5656855A

公开(公告)日：1997-08-12

申请号：US463961

申请日：1995-06-05

申请人： Katsuya Fukase ,  Takahiro Iijima ,  Masao Nakazawa ,  Shinichi Wakabayashi

发明人： Katsuya Fukase ,  Takahiro Iijima ,  Masao Nakazawa ,  Shinichi Wakabayashi

IPC分类号： H01L23/50 ,  H01L21/48 ,  H01L23/495 ,  H05K3/20 ,  H05K3/34 ,  H01L23/48

CPC分类号： H01L21/4821 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/181 ,  H05K3/20 ,  H05K3/202 ,  H05K3/205 ,  H05K3/3421

摘要： In a method for manufacturing a lead frame, a predetermined pattern is formed on a matrix 10 by a resist, an electro-deposition portion is provided in a cavity formed in the resist patterns 12, and the electro-deposition pattern 13 is separated from the matrix 10. The resist pattern is formed on the matrix 10 so that a cavity portion 17 connecting a plurality of cavity 16 ends for inner lead formation can be included in the resist pattern, and an electro-deposition portion is provided into the cavity portion 17 so that the electro-deposition pattern 13 can be formed into a configuration in which the tip ends of the inner leads 22 are connected by a connecting piece 21, and the electro-deposition pattern 13 is separated from the matrix 10 while the tip ends of the inner leads 22 are connected by the connecting piece 21.

摘要翻译： 在引线框架的制造方法中，通过抗蚀剂在矩阵10上形成预定图案，在形成于抗蚀剂图案12的空腔中设置电沉积部，并将电沉积图案13从 抗蚀剂图案形成在矩阵10上，使得连接多个腔16的端部用于内引线形成的空腔部分17可以包括在抗蚀剂图案中，并且电沉积部分被设置到空腔部分17中 使得电沉积图案13可以形成为通过连接片21连接内引线22的末端的结构，并且电沉积图案13与基体10分离，同时末端 内引线22由连接片21连接。

公开(公告)号：US5183711A

公开(公告)日：1993-02-02

申请号：US706155

申请日：1991-05-28

申请人： Norio Wada ,  Katsuya Fukase ,  Hirofumi Uchida

发明人： Norio Wada ,  Katsuya Fukase ,  Hirofumi Uchida

IPC分类号： H01L23/495 ,  H05K1/02

CPC分类号： H01L23/49572 ,  H01L2924/0002 ,  H05K1/0218 ,  Y10T428/12361 ,  Y10T428/12569

摘要： A TAB tape or tape-like carrier used for an automatic bonding process when manufacturing high-frequency semiconductor devices has a plurality of electrically conductive circuit patterns on a flexible insulative film having a plurality of holes located in gaps between adjacent circuit patterns. A ground layer is formed on a back surface of the insulative film, and electrically conductive layers or material are formed on inner peripherals walls of the holes or filled in the holes, so that the ground layer is electrically connected to the respective condcutive layers or material.

摘要翻译： 在制造高频半导体器件时用于自动接合工艺的TAB带或带状载体在柔性绝缘膜上具有多个导电电路图案，该柔性绝缘膜具有位于相邻电路图案之间的间隙中的多个孔。 在绝缘膜的后表面上形成接地层，并且在孔的内周壁上形成导电层或材料，或填充在孔中，使得接地层与相应的固化层或材料电连接 。

公开(公告)号：US08161636B2

公开(公告)日：2012-04-24

申请号：US12272048

申请日：2008-11-17

申请人： Kishio Yokouchi ,  Hideaki Yoshimura ,  Katsuya Fukase

发明人： Kishio Yokouchi ,  Hideaki Yoshimura ,  Katsuya Fukase

IPC分类号： H01K3/10

CPC分类号： H05K1/0366 ,  H05K3/445 ,  H05K3/4641 ,  H05K2201/0278 ,  H05K2201/029 ,  H05K2201/0323 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A circuit board has plated through holes which are laid out with a fine pitch and meets requirements relating to characteristics such as the thermal expansion coefficient of the circuit board. A method of manufacturing a circuit board includes: a step of forming a core portion by thermal compression bonding prepregs which include first fibers that conduct electricity and second fibers that do not conduct electricity, which have the second fibers disposed at positions where plated through holes will pass through, and which are impregnated with resin; a step of forming through holes at positions in the core portion where the second fibers are disposed; and a step of forming a conductive layer on inner surfaces of the through holes to form plated through holes at positions that do not interfere with the first fibers and thereby produce a core substrate.

摘要翻译： 电路板具有以细间距布置的电镀通孔，并满足与电路板的热膨胀系数等特性相关的要求。 一种制造电路板的方法包括：通过热压接预浸料形成芯部的步骤，该预浸料包括导电的第一纤维和不导电的第二纤维，其中第二纤维布置在镀通孔的位置 通过，并用树脂浸渍; 在设置有第二纤维的芯部中的位置形成通孔的工序; 以及在通孔的内表面上形成导电层的步骤，在不干扰第一纤维的位置处形成电镀通孔，从而制造芯基板。

公开(公告)号：US20090095520A1

公开(公告)日：2009-04-16

申请号：US12247471

申请日：2008-10-08

申请人： Katsuya Fukase ,  Kishio Yokouchi ,  Hideaki Yoshimura

发明人： Katsuya Fukase ,  Kishio Yokouchi ,  Hideaki Yoshimura

IPC分类号： H05K1/11 ,  H05K3/00

CPC分类号： H05K3/445 ,  H05K1/056 ,  H05K3/4046 ,  H05K3/4602 ,  H05K3/4608 ,  H05K2201/0323 ,  H05K2201/09827 ,  H05K2201/10234 ,  H05K2201/10416 ,  Y10T29/49124

摘要： There is provided a wiring substrate. The wiring substrate includes: a core substrate formed of a conductive material and having a through hole therein; an insulating layer formed on first and second surfaces of the core substrate; wiring patterns formed on the first and second surfaces via the insulating layer; and a via formed in the through hole and electrically connected to the wiring patterns. The via includes: a conductor ball and a conductor portion. The conductor ball has a conductive surface and an insulating member covering the conductive surface. A portion of the conductive surface is exposed from the insulating member. The conductor portion is electrically connected to the exposed conductive surface and the wiring patterns. At least one of the insulating member and the insulating layer is interposed between the via and the core substrate.

摘要翻译： 提供了布线基板。 布线基板包括：由导电材料形成并在其中具有通孔的芯基板; 绝缘层，形成在所述芯基板的第一和第二表面上; 通过绝缘层在第一和第二表面上形成的布线图案; 以及形成在通孔中并且电连接到布线图案的通孔。 通孔包括：导体球和导体部分。 导体球具有导电表面和覆盖导电表面的绝缘构件。 导电表面的一部分从绝缘构件露出。 导体部分电连接到暴露的导电表面和布线图案。 绝缘构件和绝缘层中的至少一个介于通路和芯基板之间。

公开(公告)号：US07388293B2

公开(公告)日：2008-06-17

申请号：US11151193

申请日：2005-06-14

申请人： Katsuya Fukase ,  Shinichi Wakabayashi

发明人： Katsuya Fukase ,  Shinichi Wakabayashi

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L23/147 ,  H01L21/6835 ,  H01L23/14 ,  H01L23/3677 ,  H01L23/492 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/0401

摘要： An interposer to be interposed between a semiconductor chip to be mounted thereon and a packaging board has an interposer portion made of a semiconductor material and an interposer portion provided around the foregoing interposer portion integrally therewith. On both surfaces of the interposer portions, wiring patterns are formed via insulating layers. The wiring patterns are electrically connected via through holes formed at required positions in the interposer portions. The outer interposer portion is made of an insulator or a metal body. Further, external connection terminals are bonded to one surface of the interposer.

摘要翻译： 插入在要安装在其上的半导体芯片与封装板之间的插入器具有由半导体材料制成的插入件部分和与其整体设置在所述插入件部分周围的插入部分。 在内插器部分的两个表面上，经由绝缘层形成布线图案。 布线图案通过形成在插入件部分中的所需位置的通孔电连接。 外部插入部由绝缘体或金属体构成。 此外，外部连接端子被接合到插入器的一个表面。

公开(公告)号：US20070181994A1

公开(公告)日：2007-08-09

申请号：US10598524

申请日：2005-03-02

申请人： Katsuya Fukase ,  Toyoaki Sakai ,  Munetoshi Irisawa ,  Toyokazu Komuro ,  Yasuo Kaneda ,  Masanori Natsuka ,  Wakana Aizawa

发明人： Katsuya Fukase ,  Toyoaki Sakai ,  Munetoshi Irisawa ,  Toyokazu Komuro ,  Yasuo Kaneda ,  Masanori Natsuka ,  Wakana Aizawa

IPC分类号： H01L23/12 ,  H01L21/00

CPC分类号： H05K3/064 ,  H05K1/116 ,  H05K3/0094 ,  H05K3/061 ,  H05K3/065 ,  H05K3/108 ,  H05K3/421 ,  H05K3/427 ,  H05K2201/09381 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/098 ,  H05K2203/0517 ,  H05K2203/0577 ,  H05K2203/0582 ,  H05K2203/1184 ,  H05K2203/1394

摘要： As means for solving a problem of a positional shift of a land and a hole which is caused by an alignment in the formation of an etching resist layer and a plated resist layer in a method of manufacturing a circuit board, there are provided a method of manufacturing a circuit board including the steps of forming a first resin layer on a surface of an insulating substrate having a conductive layer on the surface and an internal wall of a through hole or/and a non-through hole, forming a second resin layer which is insoluble or slightly soluble in a developing solution for the first resin layer on the first resin layer provided on the surface conductive layer, and removing the first resin layer provided over the hole with the developing solution for the first resin layer, and a method of manufacturing a circuit board including the step of uniformly charging a surface of the first resin layer to induce a potential difference to the first resin layer provided over the hole and the first resin layer provided on the surface conductive layer before forming the second resin layer. Moreover, there is provided a circuit board having a hole with a small positional shift and high precision.

摘要翻译： 作为在电路基板的制造方法中解决在形成抗蚀剂层和电镀抗蚀剂层时的取向引起的焊盘和孔的位置偏移的问题的方法，提供了一种方法， 制造电路板，包括以下步骤：在表面上具有导电层的绝缘基板的表面上形成第一树脂层和通孔或/或非通孔的内壁，形成第二树脂层，所述第二树脂层 在设置在表面导电层上的第一树脂层上的第一树脂层的显影液中不溶或微溶，用第一树脂层的显影液除去设在孔上的第一树脂层， 制造电路板，包括对第一树脂层的表面均匀充电以对设置在孔上的第一树脂层引起电位差的步骤， 在形成第二树脂层之前，在表面导电层上设置阴极层。 此外，提供一种电路板，其具有位置偏移小且精度高的孔。

公开(公告)号：US07005241B2

公开(公告)日：2006-02-28

申请号：US10822825

申请日：2004-04-13

申请人： Katsuya Fukase ,  Toyoaki Sakai

发明人： Katsuya Fukase ,  Toyoaki Sakai

IPC分类号： G03F7/00

CPC分类号： G03F7/0035 ,  H01L21/4828 ,  H01L21/4846 ,  H05K3/062 ,  H05K3/064 ,  H05K3/202 ,  H05K2203/0369 ,  H05K2203/0508 ,  H05K2203/058 ,  H05K2203/0597 ,  H05K2203/1476

摘要： A process for making a circuit board comprises the following steps of: half-etching a metal layer formed on an insulating substrate by means of a first masking which is positioned on an upper surface of the metal layer; applying a positive liquid resist on the half-etched metal layer from an upper side of the first masking; exposing the positive liquid resist with parallel light from the upper side of the first masking and developing the positive liquid resist in such a manner that a part of the positive liquid resist located under the first masking is protected to be unexposed and undeveloped; etching again the metal layer by means of a second masking composed of the first masking and the protected positive liquid resist to form a conductive pattern on the insulating substrate; and removing the first masking and the second masking from the metal layer.

摘要翻译： 制造电路板的方法包括以下步骤：通过位于金属层的上表面上的第一掩模半蚀刻在绝缘基板上形成的金属层; 从第一掩模的上侧在半蚀刻金属层上施加正的液体抗蚀剂; 以平行的光从第一掩模的上侧露出正的液体抗蚀剂，并以这样的方式显影出正的液体抗蚀剂，使得位于第一掩蔽下的正极抗蚀剂的一部分被保护为未曝光和未显影; 通过由第一掩模和受保护的正性液体抗蚀剂构成的第二掩模再次蚀刻金属层，以在绝缘基板上形成导电图案; 以及从金属层去除第一掩蔽和第二掩蔽。

公开(公告)号：US07999193B2

公开(公告)日：2011-08-16

申请号：US12247471

申请日：2008-10-08

申请人： Katsuya Fukase ,  Kishio Yokouchi ,  Hideaki Yoshimura

发明人： Katsuya Fukase ,  Kishio Yokouchi ,  Hideaki Yoshimura

IPC分类号： H05K1/11

CPC分类号： H05K3/445 ,  H05K1/056 ,  H05K3/4046 ,  H05K3/4602 ,  H05K3/4608 ,  H05K2201/0323 ,  H05K2201/09827 ,  H05K2201/10234 ,  H05K2201/10416 ,  Y10T29/49124

摘要： There is provided a wiring substrate. The wiring substrate includes: a core substrate formed of a conductive material and having a through hole therein; an insulating layer formed on first and second surfaces of the core substrate; wiring patterns formed on the first and second surfaces via the insulating layer; and a via formed in the through hole and electrically connected to the wiring patterns. The via includes: a conductor ball and a conductor portion. The conductor ball has a conductive surface and an insulating member covering the conductive surface. A portion of the conductive surface is exposed from the insulating member. The conductor portion is electrically connected to the exposed conductive surface and the wiring patterns. At least one of the insulating member and the insulating layer is interposed between the via and the core substrate.

摘要翻译： 提供了布线基板。 布线基板包括：由导电材料形成并在其中具有通孔的芯基板; 绝缘层，形成在所述芯基板的第一和第二表面上; 通过绝缘层在第一和第二表面上形成的布线图案; 以及形成在通孔中并且电连接到布线图案的通孔。 通孔包括：导体球和导体部分。 导体球具有导电表面和覆盖导电表面的绝缘构件。 导电表面的一部分从绝缘构件露出。 导体部分电连接到暴露的导电表面和布线图案。 绝缘构件和绝缘层中的至少一个介于通路和芯基板之间。