公开(公告)号：US09666540B2

公开(公告)日：2017-05-30

申请号：US14973946

申请日：2015-12-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Frederick R. Dahilig ,  Zigmund R. Camacho ,  Lionel Chien Hui Tay ,  Dioscoro A. Merilo

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/36 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/433 ,  H01L23/34 ,  H01L21/48 ,  H01L21/78 ,  H01L23/367

CPC classification number: H01L23/562 ,  H01L21/4871 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/3672 ,  H01L23/4334 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.

公开(公告)号：US09589876B2

公开(公告)日：2017-03-07

申请号：US14011491

申请日：2013-08-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Lionel Chien Hui Tay ,  Henry D. Bathan ,  Dioscoro A. Merilo ,  Jeffrey D. Punzalan

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/28 ,  H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L21/683 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/24 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24145 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/83005 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps.

Abstract translation: 通过在铜载体上形成焊料凸块制成半导体器件。 在铜载体中形成焊接捕获压痕以接收焊料凸块。 使用芯片附着粘合剂将半导体管芯安装到铜载体上。 半导体管芯具有形成在其有源表面上的接触焊盘。 封装剂沉积在铜载体，焊料凸块和半导体芯片上。 去除一部分密封剂以暴露焊料凸块和接触垫。 在密封剂上形成导电层以连接焊料凸块和接触焊盘。 导电层作为再分配层工作，以将电信号从焊料凸块路由到接触焊盘。 铜载体被去除。 在导电层和密封剂之上形成绝缘层。 多个半导体器件可以堆叠并通过焊料凸块电连接。

公开(公告)号：US20130256866A1

公开(公告)日：2013-10-03

申请号：US13906667

申请日：2013-05-31

Applicant: STATS ChipPAC, Ltd.

Inventor： Frederick R. Dahilig ,  Zigmund R. Camacho ,  Lionel Chien Hui Tay ,  Dioscoro A. Merilo

IPC: H01L23/34 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/4871 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/3672 ,  H01L23/4334 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.

Abstract translation: 通过将预制散热器框架安装在临时衬底上来制造半导体器件。 散热器框架包括平板上的垂直体。 将半导体管芯安装到散热器框架上用于散热。 在垂直体和半导体管芯周围沉积密封剂，同时留下露出的半导体管芯上的接触焊盘。 可以使用晶片级直接/顶栅模制工艺或晶片级膜辅助模制工艺来沉积密封剂。 在半导体管芯上形成互连结构。 互连结构包括形成在半导体管芯上的第一导电层，形成在第一导电层上的绝缘层，以及形成在第一导电层和绝缘层上的第二导电层。 去除临时衬底，将切割带施加到散热器框架，并且半导体管芯被切割。

公开(公告)号：US20130154076A1

公开(公告)日：2013-06-20

申请号：US13766646

申请日：2013-02-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Dioscoro A. Merilo ,  Henry D. Bathan ,  Emmanuel A. Espiritu

IPC: H01L23/495

CPC classification number: H01L23/495 ,  H01L21/4832 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/16225 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48157 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/831 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H05K2203/0384 ,  H01L2924/01014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81805 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.

Abstract translation: 半导体器件具有衬底，其具有通过衬底形成的多个导电通孔和形成在衬底上的第一导电层。 第一半导体管芯安装在衬底上。 第二半导体管芯可以安装在第一半导体管芯上。 引线框架插入件具有基板和从基板延伸的多个基底引线。 在与基极相对的基板的表面上形成耐蚀刻导电层。 引线框架安装在第一半导体管芯上的衬底上。 密封剂沉积在衬底和第一半导体管芯上。 去除基板，同时保持耐蚀刻导电层，并且基板的与基底引线相对的部分电绝缘基极。 在与基极相对的基板的表面上形成互连结构。

公开(公告)号：US08866275B2

公开(公告)日：2014-10-21

申请号：US13766646

申请日：2013-02-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Dioscoro A. Merilo ,  Henry D. Bathan ,  Emmanuel A. Espiritu

IPC: H01L23/495 ,  H01L21/00 ,  H01L21/56 ,  H01L25/10 ,  H01L25/03 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/495 ,  H01L21/4832 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/16225 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48157 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/831 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H05K2203/0384 ,  H01L2924/01014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81805 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.

Abstract translation: 半导体器件具有衬底，其具有通过衬底形成的多个导电通孔和形成在衬底上的第一导电层。 第一半导体管芯安装在衬底上。 第二半导体管芯可以安装在第一半导体管芯上。 引线框架插入件具有基板和从基板延伸的多个基底引线。 在与基极相对的基板的表面上形成耐蚀刻导电层。 引线框架安装在第一半导体管芯上的衬底上。 密封剂沉积在衬底和第一半导体管芯上。 去除基板，同时保持耐蚀刻导电层，并且基板的与基底引线相对的部分电绝缘基极。 在与基极相对的基板的表面上形成互连结构。

公开(公告)号：US20130341789A1

公开(公告)日：2013-12-26

申请号：US14011491

申请日：2013-08-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Lionel Chien Hui Tay ,  Henry D. Bathan ,  Dioscoro A. Merilo ,  Jeffrey D. Punzalan

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/24 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24145 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/83005 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps.

Abstract translation: 通过在铜载体上形成焊料凸块制成半导体器件。 在铜载体中形成焊接捕获压痕以接收焊料凸块。 使用芯片附着粘合剂将半导体管芯安装到铜载体上。 半导体管芯具有形成在其有源表面上的接触焊盘。 封装剂沉积在铜载体，焊料凸块和半导体芯片上。 去除一部分密封剂以暴露焊料凸块和接触垫。 在密封剂上形成导电层以连接焊料凸块和接触焊盘。 导电层作为再分配层工作，以将电信号从焊料凸块路由到接触焊盘。 铜载体被去除。 在导电层和密封剂上形成绝缘层。 多个半导体器件可以堆叠并通过焊料凸块电连接。

公开(公告)号：US09337161B2

公开(公告)日：2016-05-10

申请号：US14340436

申请日：2014-07-24

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Dioscoro A. Merilo ,  Henry Descalzo Bathan ,  Lionel Chien Hui Tay

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10 ,  H01L23/28 ,  H01L21/683

CPC classification number: H01L24/11 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2224/16145 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/48247 ,  H01L2224/4899 ,  H01L2224/49 ,  H01L2224/731 ,  H01L2224/732 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8101 ,  H01L2224/81011 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2224/81986 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2224/85951 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/37 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2224/13 ,  H01L2224/45 ,  H01L2924/00012

Abstract: A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Abstract translation: 集成电路封装系统的制造方法包括：将第一管芯附接到第一管芯焊盘; 通过位于所述第一管芯和所述第二管芯之间的管芯互连件将第二管芯电连接到所述第一管芯; 将与所述第一管芯焊盘相邻的第一引线连接到所述第一管芯; 将第二引线连接到所述第二管芯，所述第二引线与所述第一引线相对并且邻近所述第二管芯; 以及在所述第一裸片，所述第二裸片，芯片互连，所述第一引线和所述第二引线周围提供模制材料，所述第一引线的一部分被暴露。

公开(公告)号：US20160104681A1

公开(公告)日：2016-04-14

申请号：US14973946

申请日：2015-12-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Frederick R. Dahilig ,  Zigmund R. Camacho ,  Lionel Chien Hui Tay ,  Dioscoro A. Merilo

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48 ,  H01L23/367 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/4871 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/3672 ,  H01L23/4334 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.

公开(公告)号：US20140332955A1

公开(公告)日：2014-11-13

申请号：US14340436

申请日：2014-07-24

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Dioscoro A. Merilo ,  Henry Descalzo Bathan ,  Lionel Chien Hui Tay

IPC: H01L23/00 ,  H01L23/28

CPC classification number: H01L24/11 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2224/16145 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/48247 ,  H01L2224/4899 ,  H01L2224/49 ,  H01L2224/731 ,  H01L2224/732 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8101 ,  H01L2224/81011 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2224/81986 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2224/85951 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/37 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2224/13 ,  H01L2224/45 ,  H01L2924/00012

Abstract: A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Abstract translation: 集成电路封装系统的制造方法包括：将第一管芯附接到第一管芯焊盘; 通过位于所述第一管芯和所述第二管芯之间的管芯互连件将第二管芯电连接到所述第一管芯; 将与所述第一管芯焊盘相邻的第一引线连接到所述第一管芯; 将第二引线连接到所述第二管芯，所述第二引线与所述第一引线相对并且邻近所述第二管芯; 以及在所述第一裸片，所述第二裸片，芯片互连，所述第一引线和所述第二引线周围提供模制材料，所述第一引线的一部分被暴露。

公开(公告)号：US09257357B2

公开(公告)日：2016-02-09

申请号：US13906667

申请日：2013-05-31

Applicant: STATS ChipPAC, Ltd.

Inventor： Frederick R. Dahilig ,  Zigmund R. Camacho ,  Lionel Chien Hui Tay ,  Dioscoro A. Merilo

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/36 ,  H01L23/34 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/433 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L21/4871 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/3672 ,  H01L23/4334 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.