公开(公告)号：US06936922B1

公开(公告)日：2005-08-30

申请号：US10672886

申请日：2003-09-26

申请人： Sung Soon Park ,  Sang Jae Jang ,  Choon Heung Lee ,  Seon Goo Lee ,  Eun Sook Sohn ,  Sung Su Park

发明人： Sung Soon Park ,  Sang Jae Jang ,  Choon Heung Lee ,  Seon Goo Lee ,  Eun Sook Sohn ,  Sung Su Park

IPC分类号： H01L23/16 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10 ,  H05K1/11 ,  H05K3/34

CPC分类号： H05K3/3436 ,  H01L23/16 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3511 ,  H05K1/111 ,  H05K2201/094 ,  H05K2201/09736 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electrical substrate useful for semiconductor packages is disclosed. The electrical substrate includes a core insulative layer. A first surface of the insulative layer has circuit patterns thereon. Some of the circuit patterns are stepped in their heights from the first surface, in that a first subportion of the circuit pattern, including a ball land, extends further from the first surface than a second subportion of the same circuit pattern, and also extends further from the first surface than a ball land of other circuit patterns. Accordingly, solder balls fused to the ball lands of the stepped circuit patterns extend further from the first surface than same-size solder balls fused to the ball lands of the non-stepped circuit patterns, thereby circumventing electrical connectivity problems that may arise from warpage of the electrical substrate.

摘要翻译： 公开了一种可用于半导体封装的电气基板。 电气基板包括芯绝缘层。 绝缘层的第一表面具有电路图案。 电路图案中的一些从第一表面上升到它们的高度，因为电路图形的第一子部分（包括球形区域）比第一表面的第一子部分比相同电路图案的第二子部分进一步延伸，并且还进一步延伸 从第一个表面比其他电路图案的球场。 因此，熔融到阶梯式电路图案的球台的焊球比与非阶梯式电路图案的球面熔合的相同尺寸的焊球相比，从第一表面延伸出来，从而避免了由于翘曲引起的电连接问题 电气基板。

公开(公告)号：US07042072B1

公开(公告)日：2006-05-09

申请号：US10212496

申请日：2002-08-02

申请人： Young Ho Kim ,  Seok Hyun Choi ,  Choon Heung Lee ,  Sung Su Park ,  Sung Soon Park

发明人： Young Ho Kim ,  Seok Hyun Choi ,  Choon Heung Lee ,  Sung Su Park ,  Sung Soon Park

IPC分类号： H01L23/02 ,  H01L21/44

CPC分类号： H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and method of producing the same has a semiconductor die having a first face and a second face. A coating material is coupled to the second face of the semiconductor die. A substrate having a cavity is provided wherein the semiconductor die is placed within the cavity. An encapsulant is used to encapsulate the second face of the semiconductor die placed in the cavity. Connection members are provided to couple the semiconductor die and the substrate in order to transfer signals between the semiconductor die and the substrate. Terminal members are couple to the substrate to connect the semiconductor package to an external device. In the semiconductor package, a thermal expansion coefficient of the coating material C and a thermal expansion coefficient of the encapsulant E should be approximately equal in value in order to limit the problems associated with warpage.

摘要翻译： 半导体封装及其制造方法具有具有第一面和第二面的半导体管芯。 涂层材料耦合到半导体管芯的第二面。 提供具有空腔的衬底，其中半导体管芯被放置在空腔内。 密封剂用于封装放置在空腔中的半导体管芯的第二面。 提供连接构件以耦合半导体管芯和衬底，以便在半导体管芯和衬底之间传输信号。 端子构件耦合到衬底以将半导体封装连接到外部设备。 在半导体封装中，为了限制与翘曲相关的问题，涂层材料C的热膨胀系数和密封剂E的热膨胀系数的值应近似相等。

公开(公告)号：US07633763B1

公开(公告)日：2009-12-15

申请号：US10766101

申请日：2004-01-28

申请人： Chul Woo Park ,  Suk Gu Ko ,  Sang Jae Jang ,  Sung Su Park ,  Choon Heung Lee

发明人： Chul Woo Park ,  Suk Gu Ko ,  Sang Jae Jang ,  Sung Su Park ,  Choon Heung Lee

IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC分类号： G06K19/07743 ,  G06K19/07724 ,  H01L2224/48091 ,  H01L2924/1815 ,  H05K1/117 ,  H05K3/284 ,  H05K2201/09036 ,  H05K2201/10159 ,  H05K2203/1316 ,  H05K2203/1572 ,  H01L2924/00014

摘要： A memory card comprising a substrate having opposed top and bottom surfaces and a plurality of terminals disposed on the bottom surface thereof. Mounted to the top surface of the substrate is at least one component which is itself electrically connected to the terminals of the substrate. Formed on the bottom surface of the substrate is a first encapsulation part. Formed on the top surface of the substrate is a second encapsulation part which encapsulates the component mounted thereto.

摘要翻译： 一种存储卡，包括具有相对的顶表面和底表面的基底和设置在其底表面上的多个端子。 安装到基板的顶表面的是至少一个本身电连接到基板的端子的部件。 形成在基板的底面上的是第一封装部。 形成在基板的顶表面上的是封装安装在其上的部件的第二封装部分。

公开(公告)号：US07201327B1

公开(公告)日：2007-04-10

申请号：US10967462

申请日：2004-10-18

申请人： Chul Woo Park ,  Sang Jae Jang ,  Sung Su Park ,  Choon Heung Lee ,  Suk Gu Ko

发明人： Chul Woo Park ,  Sang Jae Jang ,  Sung Su Park ,  Choon Heung Lee ,  Suk Gu Ko

IPC分类号： G06K19/06

CPC分类号： G06K19/077 ,  G06K19/07732 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012

摘要： A memory card comprising a die paddle having opposed, generally planar first and second die paddle surfaces and multiple peripheral edge segments. Disposed along and in spaced relation to one of the peripheral edge segments of the die paddle is a plurality of contacts, each of which has opposed, generally planar first and second contact surfaces. An inner body partially encapsulates the die paddle and the contacts, the first contact surface of each of the contacts and the first die paddle surface of the die paddle being exposed in and substantially flush with a generally planar first inner body surface of the inner body. The inner body further defines a generally planar second inner body surface which is disposed in opposed relation to the first inner body surface, the second contact surface of each of the contacts being exposed in the second inner body surface. At least one electronic circuit element is attached to the first die paddle surface and electrically connected to at least one of the contacts. An outer body partially encapsulates the inner body such that the first die paddle surface, the first contact surface of each of the contacts, the first inner body surface and the electronic circuit element are covered by the outer body, with the second inner body surface and hence the second contact surface of each of the contacts not being covered by the outer body and thus exposed.

摘要翻译： 一种存储卡，其包括具有相对的，大致平面的第一和第二管芯片表面和多个外围边缘部分的管芯焊盘。 与模板的周边边缘部分中的一个相互间隔设置有多个触点，每个触点具有相对的大致平面的第一和第二接触表面。 内部主体部分地封装管芯焊盘和触头，每个触头的第一接触表面和管芯焊盘的第一裸片焊盘表面暴露于内部主体的大致平面的第一内部主体表面并基本上与其平齐。 内体进一步限定大致平坦的第二内体表面，其以与第一内体表面相对的方式设置，每个触头的第二接触表面暴露在第二内体表面中。 至少一个电子电路元件附接到第一裸片表面并电连接到至少一个触点。 外部主体部分地封装内部主体，使得第一裸片表面，每个触点的第一接触表面，第一内部主体表面和电子电路元件被外部主体覆盖，具有第二内部主体表面和 因此每个触点的第二接触表面不被外体覆盖并因此被暴露。

公开(公告)号：US07220915B1

公开(公告)日：2007-05-22

申请号：US11060263

申请日：2005-02-17

申请人： Chul Woo Park ,  Sang Jae Jang ,  Sung Su Park ,  Choon Heung Lee ,  Suk Gu Ko

发明人： Chul Woo Park ,  Sang Jae Jang ,  Sung Su Park ,  Choon Heung Lee ,  Suk Gu Ko

IPC分类号： H05K3/28 ,  H01L23/02 ,  H01L23/495

CPC分类号： G11C29/48 ,  G11C29/1201 ,  H01L23/49855 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A memory card comprising a circuit board having opposed upper and lower circuit board surfaces, at least one test pad disposed on the upper circuit board surface, and a conductive pattern disposed on the lower circuit board surface and electrically connected to the test pad. Electrically connected to the conductive pattern of the circuit board is a leadframe which includes a plurality of leads, each of the leads having a signal pad portion. At least one electronic circuit element is attached to the lower circuit board surface and electrically connected to the leadframe and to the conductive pattern of the circuit board. A body at least partially encapsulates the circuit board, the leadframe and the electronic circuit element such that the test pad of the circuit board is exposed in an upper body surface of the body, and the signal pad portions of the leads of the leadframe are exposed in a lower body surface of the body.

摘要翻译： 一种存储卡，包括具有相对的上电路板表面和下电路板表面的电路板，设置在上电路板表面上的至少一个测试焊盘和布置在下电路板表面上并电连接到测试焊盘的导电图案。 电连接到电路板的导电图案的是引线框架，其包括多个引线，每个引线具有信号焊盘部分。 至少一个电子电路元件附接到下电路板表面并电连接到引线框架和电路板的导电图案。 主体至少部分地封装电路板，引线框架和电子电路元件，使得电路板的测试焊盘暴露在主体的上体表面中，并且引线框的引线的信号焊盘部分被暴露 在身体的下半身表面。

公开(公告)号：US06833619B1

公开(公告)日：2004-12-21

申请号：US10425134

申请日：2003-04-28

申请人： Sang Jae Jang ,  Sun Goo Lee ,  Sung Su Park ,  Sung Soon Park

发明人： Sang Jae Jang ,  Sun Goo Lee ,  Sung Su Park ,  Sung Soon Park

IPC分类号： H01L2334

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/743 ,  H01L24/83 ,  H01L2224/05599 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has a substrate comprising a resin layer of an approximate planar plate, a cavity passing through the resin layer vertically at a center area thereof, a plurality of electrically conductive patterns formed at a bottom surface of the resin layer, and a conductive plan. An adhesive layer of a predetermined thickness is formed at an upper part of an inside of the cavity. A semiconductor die is positioned inside the cavity of the substrate and has a plurality of bond pads formed at a bottom surface thereof, a bottom surface of the adhesive layer being bonded to a top surface thereof. A plurality of conductive wires for electrically connecting the bond pads of the semiconductor die to the electrically conductive patterns are formed at a bottom surface of the substrate. An encapsulant is used for covering the semiconductor die formed at the lower part of the adhesive layer, the conductive wires and the cavity. A plurality of solder balls are fused to the electrically conductive patterns, which is formed at the bottom surface of the substrate.

摘要翻译： 半导体封装具有包括近似平板的树脂层，在其中心区域垂直穿过树脂层的空腔，形成在树脂层的底面的多个导电图案的基板，以及导电图 。 在空腔的内部的上部形成预定厚度的粘合剂层。 半导体管芯位于衬底的腔内部，并且在其底表面上形成有多个接合焊盘，粘合剂层的底表面粘合到其顶表面。 在基板的底面形成有用于将半导体管芯的接合焊盘电连接到导电图案的多个导线。 密封剂用于覆盖形成在粘合剂层的下部，导电线和空腔的半导体管芯。 多个焊球与形成在基板的底面的导电图案熔合。

公开(公告)号：US08928158B2

公开(公告)日：2015-01-06

申请号：US13478138

申请日：2012-05-23

申请人： Seung Han ,  Ju Mi Kim ,  Sung Su Park ,  Eun Jung Lee

发明人： Seung Han ,  Ju Mi Kim ,  Sung Su Park ,  Eun Jung Lee

IPC分类号： H01L23/29 ,  C08L63/04 ,  C08G59/32 ,  C09D163/04 ,  C09J163/04

CPC分类号： H01L23/295 ,  C08G59/3218 ,  C08L63/04 ,  C09D163/04 ,  C09J163/04 ,  H01L2924/0002 ,  H01L2924/00

摘要： An epoxy resin composition for encapsulating a semiconductor device includes a curing agent, a curing accelerator, inorganic fillers, and an epoxy resin, the epoxy resin including a first resin represented by Formula 1: wherein R1 and R2 are each independently hydrogen or a C1 to C4 linear or branched alkyl group, and n is a value from 1 to 9 on average.

摘要翻译： 用于封装半导体器件的环氧树脂组合物包括固化剂，固化促进剂，无机填料和环氧树脂，所述环氧树脂包括由式1表示的第一树脂：其中R 1和R 2各自独立地为氢或C1至 C4直链或支链烷基，n为1〜9的平均值。

公开(公告)号：US07981237B2

公开(公告)日：2011-07-19

申请号：US11871227

申请日：2007-10-12

申请人： Sung Su Park ,  So Hyun Kim ,  Youn Sang Kim ,  Seong Won Nam ,  Kang Mu Lee

发明人： Sung Su Park ,  So Hyun Kim ,  Youn Sang Kim ,  Seong Won Nam ,  Kang Mu Lee

IPC分类号： G01N33/00

CPC分类号： B29C59/14 ,  B01L3/502707 ,  B01L2200/0668 ,  B01L2200/0689 ,  B01L2300/0825 ,  B01L2300/0887 ,  Y10T156/107 ,  Y10T156/12 ,  Y10T436/11

摘要： A micro- or nano-fluidic chip fabricated with a Norland Optical Adhesive (NOA), an acrylated polyurethane-based UV-polymerizable optical adhesive. The micro- or nano-fluidic chip has sequentially an inlet, a channel, and an outlet. The channel has a pillar in the region of the outlet to prevent beads from flowing out, and the surface of the channels in the micro- or nano-fluidic chip is hydrophilic, which generates spontaneous flow in the channels by a capillary force without any extra external pumping.

摘要翻译： 用Norland光学胶粘剂（NOA），丙烯酸酯化聚氨酯基的可UV聚合光学胶粘剂制成的微米或纳米流体碎片。 微流体芯片或纳米流体芯片依次具有入口，通道和出口。 该通道在出口区域中具有一个支柱，以防止珠子流出，并且微米或纳米流体芯片中的通道表面是亲水性的，其通过毛细管力在通道中产生自发的流动，而没有任何额外的 外部泵送。

公开(公告)号：US07843072B1

公开(公告)日：2010-11-30

申请号：US12190039

申请日：2008-08-12

申请人： Sung Su Park ,  Jin Young Kim ,  Jeong Gi Jin

发明人： Sung Su Park ,  Jin Young Kim ,  Jeong Gi Jin

IPC分类号： H01L23/48

CPC分类号： H01L24/06 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/06135 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

摘要： Disclosed is a semiconductor package. The semiconductor package is configured to form a plurality of through holes for forming a through silicon via at once using a sawing device used for wafer sawing instead of a separate laser drilling equipment or a deep reactive ion etching (DRIE) equipment. Accordingly, the semiconductor package saves fabricating time and increases fabrication yield, saves costs for a laser drilling equipment or a DRIE equipment, and prevents various defects generated in an inner portion of a through hole in the case of using the laser drilling equipment or the DRIE equipment.

摘要翻译： 公开了一种半导体封装。 半导体封装被配置为形成多个通孔，用于通过使用用于晶片锯切的锯切装置代替单独的激光钻孔设备或深反应离子蚀刻（DRIE）设备来一次形成通硅。 因此，半导体封装节省制造时间并提高制造成品率，节省了激光钻孔设备或DRIE设备的成本，并且防止在使用激光钻孔设备或DRIE的情况下通孔内部产生的各种缺陷 设备。

公开(公告)号：US09123543B1

公开(公告)日：2015-09-01

申请号：US13274877

申请日：2011-10-17

申请人： Jung Gi Jin ,  Jong Sik Paek ,  Sung Su Park ,  Seok Bong Kim ,  Tae Kyung Hwang ,  Se Woong Cha

发明人： Jung Gi Jin ,  Jong Sik Paek ,  Sung Su Park ,  Seok Bong Kim ,  Tae Kyung Hwang ,  Se Woong Cha

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device and method of manufacturing the same are provided. The semiconductor device comprises a semiconductor die including a bond pad, a redistribution layer, and a solder ball. The redistribution layer is formed by sequentially plating copper and nickel, sequentially plating nickel and copper, or sequentially plating copper, nickel, and copper. The redistribution layer includes a nickel layer in order to prevent a crack from occurring in a copper layer. Further, a projection is formed in an area of the redistribution layer or a dielectric layer to which the solder ball is welded and corresponds, so that an area of the redistribution layer to which the solder ball is welded increases, thereby increasing bonding power between the solder ball and the redistribution layer.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括具有接合焊盘，再分配层和焊球的半导体管芯。 再分配层通过依次镀铜和镍，依次电镀镍和铜，或依次镀铜，镍和铜而形成。 再分布层包括镍层以防止在铜层中发生裂纹。 此外，在再分布层或焊球对应的电介质层的区域中形成突起，使得焊球焊接的再分布层的面积增加，从而增加焊球之间的结合力 焊球和再分配层。