公开(公告)号：US08586477B2

公开(公告)日：2013-11-19

申请号：US13195128

申请日：2011-08-01

Applicant: Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

Inventor： Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

IPC: H01L21/44 ,  H01L21/00 ,  H01L23/04

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L23/481 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05609 ,  H01L2224/05613 ,  H01L2224/05614 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.

Abstract translation: 提供了具有贯通电极，半导体封装以及半导体封装的制造方法的半导体装置。 该方法包括制备包括掩埋通孔的衬底，所述埋入通孔在第一端具有第一表面，以及所述掩埋通孔从所述衬底的第一衬底表面延伸到所述衬底中; 平行化与第一衬底表面相对的衬底的第二衬底表面以通过在与第一端相对的埋置通孔的第二端处暴露第二通孔表面而形成通孔; 在通孔的暴露的第二通孔表面上形成导电覆盖层; 并且使所述第二衬底表面凹陷，使得所述通孔的至少第一部分延伸超出所述第二衬底表面。

公开(公告)号：US20120028412A1

公开(公告)日：2012-02-02

申请号：US13195128

申请日：2011-08-01

Applicant: Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

Inventor： Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

IPC: H01L21/50 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L23/481 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05609 ,  H01L2224/05613 ,  H01L2224/05614 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.

Abstract translation: 提供了具有贯通电极，半导体封装以及半导体封装的制造方法的半导体装置。 该方法包括制备包括掩埋通孔的衬底，所述埋入通孔在第一端具有第一表面，以及所述掩埋通孔从所述衬底的第一衬底表面延伸到所述衬底中; 平行化与第一衬底表面相对的衬底的第二衬底表面以通过在与第一端相对的埋置通孔的第二端处暴露第二通孔表面而形成通孔; 在通孔的暴露的第二通孔表面上形成导电覆盖层; 并且使所述第二衬底表面凹陷，使得所述通孔的至少第一部分延伸超出所述第二衬底表面。

公开(公告)号：US08637989B2

公开(公告)日：2014-01-28

申请号：US13569653

申请日：2012-08-08

Applicant: Ho-jin Lee ,  Hyun-soo Chung ,  Chang-seong Jeon ,  Sang-sick Park ,  Jae-hyun Phee

Inventor： Ho-jin Lee ,  Hyun-soo Chung ,  Chang-seong Jeon ,  Sang-sick Park ,  Jae-hyun Phee

IPC: H01L23/48

CPC classification number: H01L23/48 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941

Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.

Abstract translation: 半导体器件包括半导体衬底和通孔电极。 通孔电极在基板上具有第一部分并且朝向基板延伸并且具有从第一部分延伸到基板中的多个尖峰，每个尖峰彼此间隔开。

公开(公告)号：US20110284936A1

公开(公告)日：2011-11-24

申请号：US13108231

申请日：2011-05-16

Applicant: Ju-il CHOI ,  Jae-hyun Phee ,  Hyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

Inventor： Ju-il CHOI ,  Jae-hyun Phee ,  Hyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

IPC: H01L29/772 ,  H01L23/48

CPC classification number: H01L21/76879 ,  H01L21/76844 ,  H01L21/76873 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05009 ,  H01L2224/06181

Abstract: A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer.

Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件包括层间绝缘层图案，由形成在层间绝缘层图案中的通孔形成的通道暴露的金属线图案，以输入和输出电信号，以及直接接触金属线图案的镀层图案和 填充通孔。 该方法包括形成具有金属线图案的层间绝缘层，以输入和输出其中形成的电信号，形成通孔以限定延伸穿过层间绝缘层的通道，直到金属线图案的至少一部分露出 并且形成镀层图案以填充通孔并且通过使用通过通孔露出的金属线图案作为种子金属层直接接触金属线图案。

公开(公告)号：US08564102B2

公开(公告)日：2013-10-22

申请号：US13108231

申请日：2011-05-16

Applicant: Ju-il Choi ,  Jae-hyun Phee ,  Kyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

Inventor： Ju-il Choi ,  Jae-hyun Phee ,  Kyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76879 ,  H01L21/76844 ,  H01L21/76873 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05009 ,  H01L2224/06181

Abstract: A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer.

Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件包括层间绝缘层图案，由形成在层间绝缘层图案中的通孔形成的通道暴露的金属线图案，以输入和输出电信号，以及直接接触金属线图案的镀层图案和 填充通孔。 该方法包括形成具有金属线图案的层间绝缘层，以输入和输出其中形成的电信号，形成通孔以限定延伸穿过层间绝缘层的通道，直到金属线图案的至少一部分露出 并且形成镀层图案以填充通孔并且通过使用通过通孔露出的金属线图案作为种子金属层直接接触金属线图案。

公开(公告)号：US20120299194A1

公开(公告)日：2012-11-29

申请号：US13569653

申请日：2012-08-08

Applicant: Ho-jin Lee ,  Hyun-soo Chung ,  Chang-seong Jeon ,  Sang-sick Park ,  Jae-hyun Phee

Inventor： Ho-jin Lee ,  Hyun-soo Chung ,  Chang-seong Jeon ,  Sang-sick Park ,  Jae-hyun Phee

IPC: H01L23/48

CPC classification number: H01L23/48 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941

Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.

Abstract translation: 半导体器件包括半导体衬底和通孔电极。 通孔电极在基板上具有第一部分并且朝向基板延伸并且具有从第一部分延伸到基板中的多个尖峰，每个尖峰彼此间隔开。

公开(公告)号：US20100105169A1

公开(公告)日：2010-04-29

申请号：US12543347

申请日：2009-08-18

Applicant: Ho-jin Lee ,  Hyun-soo Chung ,  Chang-seong Jeon ,  Sang-sick Park ,  Jae-hyun Phee

Inventor： Ho-jin Lee ,  Hyun-soo Chung ,  Chang-seong Jeon ,  Sang-sick Park ,  Jae-hyun Phee

IPC: H01L21/98 ,  H01L21/768

CPC classification number: H01L23/48 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941

Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.

Abstract translation: 半导体器件包括半导体衬底和通孔电极。 通孔电极在基板上具有第一部分并且朝向基板延伸并且具有从第一部分延伸到基板中的多个尖峰，每个尖峰彼此间隔开。

公开(公告)号：US07831003B2

公开(公告)日：2010-11-09

申请号：US11722308

申请日：2005-11-11

Applicant: Sun-heul Ryoo ,  Do-seob Ahn ,  Ho-jin Lee

Inventor： Sun-heul Ryoo ,  Do-seob Ahn ,  Ho-jin Lee

IPC: H03D1/00

CPC classification number: H04L27/0014 ,  H03M13/2957 ,  H03M13/336 ,  H04L1/005 ,  H04L1/0066 ,  H04L25/067 ,  H04L27/22 ,  H04L2027/0028 ,  H04L2027/0067

Abstract: An apparatus and method for phase recovery in a wireless communication system employs independently decodable component codes. The apparatus includes a decoding unit for decoding the input signal to thereby output the decoding value; an estimation unit for estimating phase errors of the received signal by estimating phase errors of the each component codeword in the received signal to thereby generate phase error estimation values; and a correction unit for correcting the phase of received signal using the phase error estimation values to thereby generate the phase corrected signal in an effective manner.

Abstract translation: 无线通信系统中相位恢复的装置和方法采用可独立解码的分量代码。 该装置包括：解码单元，用于对输入信号进行解码，从而输出解码值; 估计单元，用于通过估计接收信号中的每个分量码字的相位误差来估计接收信号的相位误差，由此产生相位误差估计值; 以及校正单元，用于使用相位误差估计值校正接收信号的相位，从而以有效的方式产生相位校正信号。

公开(公告)号：US20090274246A1

公开(公告)日：2009-11-05

申请号：US11722308

申请日：2005-11-11

Applicant: Sun-heul Ryoo ,  Do-seob Ahn ,  Ho-jin Lee

Inventor： Sun-heul Ryoo ,  Do-seob Ahn ,  Ho-jin Lee

IPC: H04L27/06 ,  H04L7/00

CPC classification number: H04L27/0014 ,  H03M13/2957 ,  H03M13/336 ,  H04L1/005 ,  H04L1/0066 ,  H04L25/067 ,  H04L27/22 ,  H04L2027/0028 ,  H04L2027/0067

Abstract: An apparatus and method for phase recovery in a wireless communication system employs independently decodable component codes. The apparatus includes a decoding unit for decoding the input signal to thereby output the decoding value; an estimation unit for estimating phase errors of the received signal by estimating phase errors of the each component codeword in the received signal to thereby generate phase error estimation values; and a correction unit for correcting the phase of received signal using the phase error estimation values to thereby generate the phase corrected signal in an effective manner.

Abstract translation: 无线通信系统中相位恢复的装置和方法采用可独立解码的分量代码。 该装置包括：解码单元，用于对输入信号进行解码，从而输出解码值; 估计单元，用于通过估计接收信号中的每个分量码字的相位误差来估计接收信号的相位误差，由此产生相位误差估计值; 以及校正单元，用于使用相位误差估计值校正接收信号的相位，从而以有效的方式产生相位校正信号。

公开(公告)号：US20080019448A1

公开(公告)日：2008-01-24

申请号：US11779415

申请日：2007-07-18

Applicant: Sang-jo LEE ,  Ho-jin Lee ,  Do-Hyung Kim

Inventor： Sang-jo LEE ,  Ho-jin Lee ,  Do-Hyung Kim

IPC: H04N11/02

CPC classification number: H04N19/57 ,  H04N19/51 ,  H04N19/533 ,  H04N19/56

Abstract: Provided are a motion estimation apparatus and method and an image encoding apparatus and method employing the same. The motion estimation apparatus includes an optimal motion estimation unit performing motion estimation in an initial block mode while skipping remaining block modes excluding the initial block mode from a plurality of block modes of the current block, or performing motion estimation in candidate block modes determined from the plurality of block modes.

Abstract translation: 提供了一种运动估计装置和方法以及采用该运动估计装置和方法的图像编码装置和方法。 运动估计装置包括：最优运动估计单元，在从当前块的多个块模式中跳过除了初始块模式之外的剩余块模式时，以初始块模式执行运动估计，或者在从所述块模式确定的候选块模式中执行运动估计 多个块模式。