公开(公告)号：US07842541B1

公开(公告)日：2010-11-30

申请号：US12237173

申请日：2008-09-24

申请人： Sukianto Rusli ,  Ronald Patrick Huemoeller ,  Bob Shih-Wei Kuo ,  Lee John Smith

发明人： Sukianto Rusli ,  Ronald Patrick Huemoeller ,  Bob Shih-Wei Kuo ,  Lee John Smith

IPC分类号： H01L21/00

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/731 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method includes forming a substrate layer, the substrate layer including a circuit pattern having terminals and bump pads. A stiffener is formed, the stiffener including via apertures having electrically conductive via aperture sidewalls and an electronic component opening. The stiffener is attached to the substrate layer. The electrically conductive via aperture sidewalls are electrically connected to the terminals. An electronic component is mounted to the bump pads and within the electronic component opening thus minimizing the height of the package. Further, the stiffener minimizing undesirable bending of the package and acts as an internal heat sink.

摘要翻译： 一种方法包括形成衬底层，所述衬底层包括具有端子和凸块焊盘的电路图案。 加强件形成，加强件包括具有导电通孔孔侧壁和电子部件开口的通孔。 加强件附接到基底层。 导电通孔孔侧壁与端子电连接。 电子部件安装到凸块焊盘和电子部件开口内，从而最小化封装的高度。 此外，加强件最小化包装的不期望的弯曲并且充当内部散热器。

公开(公告)号：US08017436B1

公开(公告)日：2011-09-13

申请号：US11953680

申请日：2007-12-10

申请人： Ronald Patrick Huemoeller ,  Sukianto Rusli ,  Bob Shih-Wei Kuo ,  Jon Gregory Aday ,  Lee John Smith ,  Robert F. Darveaux

发明人： Ronald Patrick Huemoeller ,  Sukianto Rusli ,  Bob Shih-Wei Kuo ,  Jon Gregory Aday ,  Lee John Smith ,  Robert F. Darveaux

IPC分类号： H01L23/48 ,  H01L23/52 ,  H05K1/16

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49861 ,  H01L23/552 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L27/14618 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/83001 ,  H01L2224/85001 ,  H01L2224/92247 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of forming a package includes forming a circuit pattern on a first carrier and embedding the circuit pattern in a dielectric material on a second carrier. The first carrier is removed and a buildup dielectric material is mounted to the dielectric material and the circuit pattern. Laser-ablated artifacts are formed in the buildup dielectric material and filled with an electrically conductive material to form a buildup circuit pattern. The second carrier is patterned into a stiffener, which provides rigidity to the thin package.

摘要翻译： 形成封装的方法包括在第一载体上形成电路图案，并将电路图案嵌入到第二载体上的电介质材料中。 去除第一载体并且将积聚电介质材料安装到介电材料和电路图案。 在积聚电介质材料中形成激光烧蚀的伪影，并填充有导电材料以形成积聚电路图案。 第二载体被图案化成加强件，其为薄包装提供刚性。

公开(公告)号：US07632753B1

公开(公告)日：2009-12-15

申请号：US11867293

申请日：2007-10-04

申请人： Sukianto Rusli ,  Bob Shih-Wei Kuo ,  Ronald Patrick Huemoeller

发明人： Sukianto Rusli ,  Bob Shih-Wei Kuo ,  Ronald Patrick Huemoeller

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L23/04 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/538

CPC分类号： H01L23/525 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76879 ,  H01L23/5328 ,  H01L23/5329 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/11 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A method of forming a wafer level package includes attaching a laser-activated dielectric material to an integrated circuit substrate to form an assembly, the integrated circuit substrate including a plurality of electronic components having terminals on first surfaces thereof. The laser-activated dielectric material is laser activated and ablated with a laser to form laser-ablated artifacts in the laser-activated dielectric material and simultaneously to form an electrically conductive laser-activated layer lining the laser-ablated artifacts. The laser-ablated artifacts are filled using an electroless plating process in which an electrically conductive filler material is selectively plated on the laser-activated layer to form an embedded circuit pattern within the laser-activated dielectric material.

摘要翻译： 形成晶片级封装的方法包括将激光激活介电材料附接到集成电路基板以形成组件，所述集成电路基板包括多个电子部件，所述电子部件在其第一表面上具有端子。 激光激活的介电材料被激光激活并用激光烧蚀，以在激光激活的电介质材料中形成激光烧蚀的伪影，同时形成衬在激光烧蚀的伪像上的导电激光激活层。 使用化学镀方法填充激光烧蚀的人造物，其中导电填料材料选择性地电镀在激光激活层上，以在激光激活的电介质材料内形成嵌入的电路图案。

公开(公告)号：US08535961B1

公开(公告)日：2013-09-17

申请号：US12964397

申请日：2010-12-09

申请人： Bob Shih-Wei Kuo ,  Brett Arnold Dunlap ,  David Bolognia

发明人： Bob Shih-Wei Kuo ,  Brett Arnold Dunlap ,  David Bolognia

IPC分类号： H01L21/00

CPC分类号： H01L33/486 ,  H01L21/568 ,  H01L24/19 ,  H01L24/24 ,  H01L25/0753 ,  H01L25/167 ,  H01L33/0079 ,  H01L33/64 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/73277 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of forming a light emitting diode (LED) package includes mounting a LED structure to a carrier, overmolding the LED structure in a package body, backgrinding the package body to expose the LED structure, removing the carrier, and forming a redistribution layer (RDL) buildup structure comprising a RDL circuit pattern coupled to a LED of the LED structure. The LED package is formed without a substrate in one embodiment. By forming the LED package without a substrate, the thickness of the LED package is minimized. Further, by forming the LED package without a substrate, heat removal from the LED is maximized as is electrical performance. Further still, by forming the LED package without a substrate, the fabrication cost of the LED package is minimized.

摘要翻译： 一种形成发光二极管（LED）封装的方法，包括将LED结构安装到载体上，将封装体中的LED结构模制成二次模制，背面研磨封装体以暴露LED结构，去除载体，并形成再分布层（ RDL）积累结构，其包括耦合到LED结构的LED的RDL电路图案。 在一个实施例中，LED封装形成为没有基板。 通过形成没有基板的LED封装，LED封装的厚度最小化。 此外，通过在没有基板的情况下形成LED封装，与电气性能一样，从LED的散热最大化。 此外，通过形成没有基板的LED封装，LED封装的制造成本最小化。

公开(公告)号：US20120104629A1

公开(公告)日：2012-05-03

申请号：US13348304

申请日：2012-01-11

申请人： David Bolognia ,  Bob Shih-Wei Kuo ,  Bud Troche

发明人： David Bolognia ,  Bob Shih-Wei Kuo ,  Bud Troche

IPC分类号： H01L23/498

CPC分类号： B81B7/0061 ,  B81B7/0064 ,  B81B7/007 ,  B81B2201/0257 ,  B81B2207/012 ,  B81B2207/095 ,  H01L23/552 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/165 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.

摘要翻译： 半导体器件具有具有多个金属迹线和多个基极通孔的基底基板。 通过基底基板形成开口。 至少一个模具附接到基板的第一表面并且定位在开口上方。 盖基板具有多个金属迹线。 盖衬底中的空腔形成围绕腔的侧壁部分。 覆盖基板被附接到基底基底，使得至少一个管芯位于空腔的内部。 基底衬底中的接地平面耦合到覆盖衬底中的接地平面，以在至少一个管芯周围形成RF屏蔽。

公开(公告)号：US09013011B1

公开(公告)日：2015-04-21

申请号：US13046071

申请日：2011-03-11

申请人： Bob Shih-Wei Kuo ,  Brett Arnold Dunlap ,  Louis B. Troche, Jr. ,  Ahmer Syed ,  Russell Shumway

发明人： Bob Shih-Wei Kuo ,  Brett Arnold Dunlap ,  Louis B. Troche, Jr. ,  Ahmer Syed ,  Russell Shumway

IPC分类号： H01L23/49 ,  H01L27/04

CPC分类号： H01L27/04 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A staggered die MEMS package includes a substrate having a converter cavity formed therein. A converter electronic component is mounted within the converter cavity. Further, a MEMS electronic component is mounted to both the substrate and the converter electronic component in a staggered die arrangement. By staggering the MEMS electronic component directly on the converter electronic component instead of locating the MEMS electronic component in a side by side arrangement with the converter electronic component, the total package width of the staggered die MEMS package is minimized. Further, by locating the converter electronic component within the converter cavity and staggering the MEMS electronic component directly on the converter electronic component, the total package height, sometimes called Z-height, of the staggered die MEMS package is minimized.

摘要翻译： 交错的模具MEMS封装包括其中形成有转换器腔的衬底。 A转换器电子部件安装在转换器腔内。 此外，MEMS电子部件以交错的管芯装置安装到基板和转换器电子部件两者。 通过直接在转换器电子部件上交错MEMS电子部件，而不是将MEMS电子部件与转换器电子部件并排布置，使交错的模具MEMS封装的总封装宽度最小化。 此外，通过将转换器电子部件定位在转换器腔内并将MEMS电子部件直接交错在转换器电子部件上，交错模具MEMS封装的总封装高度（有时称为Z高度）被最小化。

公开(公告)号：US08981537B2

公开(公告)日：2015-03-17

申请号：US13348304

申请日：2012-01-11

申请人： David Bolognia ,  Bob Shih-Wei Kuo ,  Bud Troche

发明人： David Bolognia ,  Bob Shih-Wei Kuo ,  Bud Troche

IPC分类号： H01L31/0203 ,  H01L23/552 ,  B81B7/00 ,  H01L23/00 ,  H01L25/16

CPC分类号： B81B7/0061 ,  B81B7/0064 ,  B81B7/007 ,  B81B2201/0257 ,  B81B2207/012 ,  B81B2207/095 ,  H01L23/552 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/165 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.

摘要翻译： 半导体器件具有具有多个金属迹线和多个基极通孔的基底基板。 通过基底基板形成开口。 至少一个模具附接到基板的第一表面并且定位在开口上方。 盖基板具有多个金属迹线。 盖衬底中的空腔形成围绕腔的侧壁部分。 覆盖基板被附接到基底基底，使得至少一个管芯位于空腔的内部。 基底衬底中的接地平面耦合到覆盖衬底中的接地平面，以在至少一个管芯周围形成RF屏蔽。

公开(公告)号：US08115283B1

公开(公告)日：2012-02-14

申请号：US12502627

申请日：2009-07-14

申请人： David Bolognia ,  Bob Shih-Wei Kuo ,  Bud Troche

发明人： David Bolognia ,  Bob Shih-Wei Kuo ,  Bud Troche

IPC分类号： H01L23/552 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： B81B7/0061 ,  B81B7/0064 ,  B81B7/007 ,  B81B2201/0257 ,  B81B2207/012 ,  B81B2207/095 ,  H01L23/552 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/165 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.

摘要翻译： 半导体器件具有具有多个金属迹线和多个基极通孔的基底基板。 通过基底基板形成开口。 至少一个模具附接到基板的第一表面并且定位在开口上方。 盖基板具有多个金属迹线。 盖衬底中的空腔形成围绕腔的侧壁部分。 覆盖基板被附接到基底基底，使得至少一个管芯位于空腔的内部。 基底衬底中的接地平面耦合到覆盖衬底中的接地平面，以在至少一个管芯周围形成RF屏蔽。

公开(公告)号：US08809677B1

公开(公告)日：2014-08-19

申请号：US12830138

申请日：2010-07-02

申请人： Bob Shih-Wei Kuo

发明人： Bob Shih-Wei Kuo

IPC分类号： H01L31/042 ,  G02B5/10 ,  G02B5/09

CPC分类号： G02B19/0042 ,  F24S23/70 ,  F24S2023/83 ,  G02B5/09 ,  G02B5/10 ,  G02B19/0023 ,  H01L31/044 ,  H01L31/0547 ,  Y02E10/40 ,  Y02E10/52

摘要： In accordance with the present invention, there is provided multiple embodiments of a concentrated photovoltaic (CPV) module. In each embodiment of the present invention, the CPV module includes a light guide having a molded, cast or machined hollow funnel with a highly reflective internal surface for use in guiding focused solar rays to the active, front surface of the receiver die of the CPV module.

摘要翻译： 根据本发明，提供了集中光伏（CPV）模块的多个实施例。 在本发明的每个实施例中，CPV模块包括具有模制的，铸造或机加工的中空漏斗的导光体，其具有高度反射的内表面，用于将聚焦的太阳光线引导到CPV的接收器芯片的有源的前表面 模块。

公开(公告)号：US08671565B1

公开(公告)日：2014-03-18

申请号：US12800757

申请日：2010-05-21

申请人： Bob Shih-Wei Kuo

发明人： Bob Shih-Wei Kuo

IPC分类号： H01R43/00 ,  H05K13/00

CPC分类号： H05K1/116 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/045 ,  H05K3/107 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/2072 ,  Y10T29/49128 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49171 ,  Y10T29/49176 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A capture pad structure includes a lower dielectric layer, a capture pad embedded within the lower dielectric layer, the capture pad comprising a plurality of linear segments. To form the capture pad, a focused laser beam is moved linearly to form linear channels in the dielectric layer. These channels are filled with an electrically conductive material to form the capture pad.

摘要翻译： 捕获垫结构包括下介电层，嵌入在下介电层内的捕获垫，捕获垫包括多个线性段。 为了形成捕获垫，聚焦的激光束线性地移动以在介电层中形成线性通道。 这些通道填充有导电材料以形成捕获垫。