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    Semiconductor package, method of production of same, and semiconductor device
    2.
    发明授权
    Semiconductor package, method of production of same, and semiconductor device 有权
    半导体封装，其制造方法和半导体器件

    公开(公告)号：US07314780B2

    公开(公告)日：2008-01-01

    申请号：US11145924

    申请日：2005-06-07

    申请人： Noriyoshi Shimizu ,  Akio Rokugawa ,  Takahiro Iijima

    发明人： Noriyoshi Shimizu ,  Akio Rokugawa ,  Takahiro Iijima

    IPC分类号： H01L23/48

    CPC分类号： H05K1/162 ,  H01L23/49822 ,  H01L23/49833 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09763 ,  H05K2203/135 ,  H01L2224/05599

    摘要： A semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, wherein a topmost stacked structure of the multilayer interconnect structure includes a capacitor structure, the capacitor structure having a dielectric layer comprised of a mixed electrodeposited layer of high dielectric constant inorganic filler and insulating resin and including chip connection pads for directly connecting top electrodes and bottom electrodes with electrodes of the semiconductor chip, whereby greater freedom in design of interconnect patterns can be secured, the degree of proximity of the capacitor and semiconductor chip can be greatly improved, and the package can be made smaller and lighter in weight, a method of production of the same, and a semiconductor device using this semiconductor package.

    摘要翻译： 一种半导体封装，其具有多层互连结构，用于将半导体芯片安装在其顶表面上，其中所述多层互连结构的最上层堆叠结构包括电容器结构，所述电容器结构具有介电层，所述电介质层由混合电沉积层 高介电常数无机填料和绝缘树脂，并且包括用于直接连接具有半导体芯片电极的顶电极和底电极的芯片连接焊盘，从而可以确保互连图案设计的更大自由度，电容器和半导体芯片的接近程度 可以大大改善，并且可以使包装重量更小更轻，其制造方法以及使用该半导体封装的半导体器件。

    Method of production of semiconductor package
    7.
    发明授权
    Method of production of semiconductor package 有权
    半导体封装的生产方法

    公开(公告)号：US07033934B2

    公开(公告)日：2006-04-25

    申请号：US10693374

    申请日：2003-10-24

    申请人： Takahiro Iijima ,  Akio Rokugawa

    发明人： Takahiro Iijima ,  Akio Rokugawa

    IPC分类号： H01L21/44

    CPC分类号： H05K1/0222 ,  H01L23/49827 ,  H01L23/642 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01078 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/115 ,  H05K1/162 ,  H05K3/4046 ,  H05K2201/09809

    摘要： A semiconductor package of superior high frequency characteristics enabling easy mounting of a large-sized capacitor and thereby enabling fluctuation of the power supply voltage to be suppressed and enabling a reduction of the inductance of the wiring portion connecting the capacitor and a connection terminal, that is, a semiconductor package mounting a capacitor for suppressing fluctuation of a power supply voltage, wherein the capacitor is comprised of, in an attachment hole passing through the board in the thickness direction, a conductor wire to be connected to a connection terminal of a semiconductor chip at one end, a high dielectric constant material covering the conductor wire at a predetermined thickness, and a conductor layer arranged between the outer circumference of the high dielectric constant material and the inner wall of the attachment hole, provided as a coaxial structure having the conductor wire at its center, and a method of production of the same.

    摘要翻译： 具有优异的高频特性的半导体封装，能够容易地安装大型电容器，从而能够抑制电源电压的波动，并且能够降低连接电容器和连接端子的布线部分的电感，即 ，安装用于抑制电源电压波动的电容器的半导体封装，其中，所述电容器包括：在厚度方向穿过所述板的安装孔中，连接到半导体芯片的连接端子的导线 一端覆盖预定厚度的导体线的高介电常数材料，以及设置在高介电常数材料的外周与安装孔的内壁之间的导体层，其设置为具有导体的同轴结构 其中心线及其制造方法。

    Build-up board package for semiconductor devices
    9.
    发明授权
    Build-up board package for semiconductor devices 有权
    用于半导体器件的堆叠板封装

    公开(公告)号：US06340841B2

    公开(公告)日：2002-01-22

    申请号：US09488087

    申请日：2000-01-20

    申请人： Takahiro Iijima ,  Akio Rokugawa

    发明人： Takahiro Iijima ,  Akio Rokugawa

    IPC分类号： H01L23053

    CPC分类号： H05K1/114 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09845 ,  H05K2201/10734 ,  H01L2924/00

    摘要： A package for semiconductor devices, comprising a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a conductor segment penetrating the core board; a front side laminate of upper wiring patterns with intermediate insulating layers intervening therebetween on the front side base wiring pattern, in which each adjacent pair of the upper wiring patterns are electrically connected to each other through a via plated coating on a side wall of viaholes penetrating one of the intermediate insulating layers that intervenes between the adjacent pair and in which an outermost one of the upper wiring patterns is patterned for electrical connection to a semiconductor chip; a back side laminate of insulating layers on the back side base wiring pattern; an external connection wiring pattern including external connection terminals on the back side laminate of insulating layers; wherein the external connection wiring pattern is electrically connected to the back side base wiring pattern through a via penetrating the back side laminate of insulating layers.

    摘要翻译： 一种用于半导体器件的封装，包括：芯板，其具有形成在其上的前侧基部布线图案的正面和形成在其上的背面基底布线图案的背面，所述前侧布线图案和所述背面布线图案彼此电连接 通过穿透核心板的导体段; 上侧布线图案与前侧基布线图案之间介于其间的中间绝缘层的上侧布线图案的前侧层压体，其中每个相邻的一对上布线图案通过贯通孔的侧壁上的通孔镀层彼此电连接 介于相邻对之间的中间绝缘层之一，其中最上面的一个上布线图案被图案化以与半导体芯片电连接; 背面基底布线图案上的绝缘层的背面层压体; 绝缘层的背面叠层体上具有外部连接端子的外部连接布线图案; 其中所述外部连接布线图案通过穿过绝缘层的背面层叠体的通孔电连接到所述背面基底布线图案。