公开(公告)号：US20130119393A1

公开(公告)日：2013-05-16

申请号：US13294903

申请日：2011-11-11

申请人： TingGang Zhu ,  Anup Bhalla ,  Ping Huang ,  Yueh-se Ho

发明人： TingGang Zhu ,  Anup Bhalla ,  Ping Huang ,  Yueh-se Ho

IPC分类号： H01L29/20 ,  H01L29/06 ,  H01L21/20

CPC分类号： H01L29/872 ,  H01L21/0217 ,  H01L21/0254 ,  H01L21/28581 ,  H01L21/30612 ,  H01L21/31111 ,  H01L21/56 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L25/18 ,  H01L27/0248 ,  H01L27/0814 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/405 ,  H01L29/417 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/861 ,  H01L29/8611 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05016 ,  H01L2224/05567 ,  H01L2224/11616 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.

摘要翻译： 使用绝缘基板形成垂直导电氮化物基肖特基二极管，绝缘基板在二极管器件用晶片级模塑料封装在前侧之后被提起。 晶片级成型复合体在二极管器件的前侧提供结构支撑，以允许绝缘基板被提起，使得可以在作为阴极的二极管器件的背面上形成导电层。 因此实现了基于垂直导电氮化物的肖特基二极管。 在另一个实施例中，用于垂直GaN肖特基二极管的保护电路采用与GaN肖特基二极管并联连接的硅基垂直PN结二极管，以转移反向偏置雪崩电流。

公开(公告)号：US08772144B2

公开(公告)日：2014-07-08

申请号：US13294903

申请日：2011-11-11

申请人： TingGang Zhu ,  Anup Bhalla ,  Ping Huang ,  Yueh-se Ho

发明人： TingGang Zhu ,  Anup Bhalla ,  Ping Huang ,  Yueh-se Ho

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/872 ,  H01L21/0217 ,  H01L21/0254 ,  H01L21/28581 ,  H01L21/30612 ,  H01L21/31111 ,  H01L21/56 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L25/18 ,  H01L27/0248 ,  H01L27/0814 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/405 ,  H01L29/417 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/861 ,  H01L29/8611 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05016 ,  H01L2224/05567 ,  H01L2224/11616 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.

摘要翻译： 使用绝缘基板形成垂直导电氮化物基肖特基二极管，绝缘基板在二极管器件用晶片级模塑料封装在前侧之后被提起。 晶片级成型复合体在二极管器件的前侧提供结构支撑，以允许绝缘基板被提起，使得可以在作为阴极的二极管器件的背面上形成导电层。 因此实现了基于垂直导电氮化物的肖特基二极管。 在另一个实施例中，用于垂直GaN肖特基二极管的保护电路采用与GaN肖特基二极管并联连接的硅基垂直PN结二极管，以转移反向偏置雪崩电流。

公开(公告)号：US08987878B2

公开(公告)日：2015-03-24

申请号：US12916086

申请日：2010-10-29

申请人： Tao Feng ,  Zhiqiang Niu ,  Yuping Gong ,  Ruisheng Wu ,  Ping Huang ,  Lei Shi ,  Yueh-Se Ho

发明人： Tao Feng ,  Zhiqiang Niu ,  Yuping Gong ,  Ruisheng Wu ,  Ping Huang ,  Lei Shi ,  Yueh-Se Ho

IPC分类号： H01L23/495 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L29/06

CPC分类号： H01L21/6836 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76897 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/495 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/73 ,  H01L24/94 ,  H01L25/50 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/051 ,  H01L2224/05139 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/0616 ,  H01L2224/06181 ,  H01L2224/1184 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.

摘要翻译： 无基底复合功率半导体器件可以包括薄衬底和位于衬底顶表面上的顶金属层。 衬底和外延层的总厚度可以小于25微米。 焊料凸块形成在顶部金属层的顶部，并且模塑料围绕焊料凸起并且使焊料凸块至少部分暴露。

公开(公告)号：US20130210195A1

公开(公告)日：2013-08-15

申请号：US13547358

申请日：2012-07-12

申请人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

发明人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

IPC分类号： H01L21/78

CPC分类号： H01L21/563 ,  H01L23/3157 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/13091 ,  H01L2924/00

摘要： A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

摘要翻译： WLCSP方法包括：在芯片的焊盘上沉积金属凸块; 在晶片的前表面形成第一包装层以覆盖金属凸块，同时在晶片边缘形成未覆盖的环，以露出位于两个相邻芯片之间的每个划线的端部; 稀释第一包装层以暴露金属凸块; 通过沿着未被覆盖的环的前表面上暴露的划线的两端延伸的直线切割沿着每个划线在第一包装层的前表面上形成凹槽; 研磨晶片的后表面以在晶片的边缘处形成凹陷空间和支撑环; 在凹陷空间中在晶片的底面沉积金属层; 切断晶片的边缘部分; 以及通过沿着沟槽切割第一包装层，晶片和金属层，从晶片分离单个芯片。

公开(公告)号：US20130130443A1

公开(公告)日：2013-05-23

申请号：US13302219

申请日：2011-11-22

申请人： Jun Lu ,  Alex Niu ,  Yueh-Se Ho ,  Ping Huang ,  Jacky Gong ,  Yan Xun Xue ,  Xiaotian Zhang ,  Ming-Chen Lu

发明人： Jun Lu ,  Alex Niu ,  Yueh-Se Ho ,  Ping Huang ,  Jacky Gong ,  Yan Xun Xue ,  Xiaotian Zhang ,  Ming-Chen Lu

IPC分类号： H01L21/78

CPC分类号： H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/03009 ,  H01L2224/0332 ,  H01L2224/0384 ,  H01L2224/03848 ,  H01L2224/03849 ,  H01L2224/04034 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05794 ,  H01L2224/058 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06135 ,  H01L2224/06164 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40247 ,  H01L2224/73263 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/053 ,  H01L2924/014 ,  H01L2924/00

摘要： The invention generally relates to a packaging method of an ultra-thin chip, more specifically, the invention relates to a method for packaging the ultra-thin chip with solder ball thermo-compression in wafer level packaging process. The method starts with disposing solder balls on metal pads arranged on the front surface of semiconductor chips that are formed at the front surface of a semiconductor wafer. The solder balls are soften by heating the wafer, a compression plate is applied with a pressure on the top ends of the solder balls thus forming a co-planar top surface at the top ends of the solder balls. A molding compound is deposited on the front surface of the wafer with the top ends of the solder balls exposed. The wafer is then ground from its back surface to reduce its thickness to achieve ultra-thin chip.

摘要翻译： 本发明一般涉及超薄芯片的封装方法，更具体地说，本发明涉及一种用于在晶片级封装工艺中封装具有焊球热压缩的超薄芯片的方法。 该方法开始于将焊球设置在形成在半导体晶片的前表面的半导体芯片的前表面上的金属焊盘上。 通过加热晶片来软化焊球，压力板在焊球的顶端施加压力，从而在焊球的顶端形成共面顶表面。 模具化合物沉积在晶片的前表面上，其中焊球的顶端被暴露。 然后将晶片从其背面研磨以减小其厚度以实现超薄芯片。

公开(公告)号：US20120032259A1

公开(公告)日：2012-02-09

申请号：US13273219

申请日：2011-10-13

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

IPC分类号： H01L29/78 ,  H01L21/283

CPC分类号： H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/781 ,  H01L2224/04105 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/051 ,  H01L2224/05562 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552

摘要： A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.

摘要翻译： 底部源极功率金属氧化物半导体场效应晶体管（MOSFET）器件包括形成在半导体芯片的第一表面上的初始绝缘层上的栅电极和源电极，以及形成在半导体芯片的第二表面上的漏电极 半导体芯片 源电极包括源极金属，形成在源极金属上的源极电极凸点和源极电极凸起顶部上的源电极金属层。 第一绝缘层覆盖栅电极。 从芯片的第二表面形成与栅电极对准的贯通孔，以将栅电极的一部分从第二表面露出。

公开(公告)号：US20160155688A9

公开(公告)日：2016-06-02

申请号：US14033140

申请日：2013-09-20

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC分类号： H01L23/495

CPC分类号： H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/16245 ,  H01L2924/13091 ,  H01L2924/00

摘要： A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

公开(公告)号：US20140242756A1

公开(公告)日：2014-08-28

申请号：US13775212

申请日：2013-02-24

申请人： Yan Xun Xue ,  Ping Huang ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Lei Shi ,  Liang Zhao ,  Ping Li Wu ,  Lei Duan ,  Yuping Gong

发明人： Yan Xun Xue ,  Ping Huang ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Lei Shi ,  Liang Zhao ,  Ping Li Wu ,  Lei Duan ,  Yuping Gong

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/73 ,  H01L2224/1184 ,  H01L2224/13101 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/29 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices.

摘要翻译： 一种用于在倒装芯片工艺中制备半导体器件的方法包括形成围绕每个半导体芯片的深槽; 沉积第一塑料封装材料以形成覆盖半导体晶片的前表面并填充深槽的第一塑料封装层; 在研磨后在半导体晶片的背面沉积金属层; 研磨金属层的最外部分，从而形成位于未被金属层覆盖的半导体晶片的边缘周围的背面的环形区域; 沿着由填充有第一塑料包装材料的每个深槽的两端形成的直线切割填充在深槽中的第一塑料封装层，半导体晶片，金属层和第一塑料封装材料; 并且拾取半导体器件并安装在衬底上，而不会翻转半导体器件。

公开(公告)号：US20120104580A1

公开(公告)日：2012-05-03

申请号：US12916086

申请日：2010-10-29

申请人： Tao Feng ,  Zhiqiang Niu ,  Yuping Gong ,  Ruisheng Wu ,  Ping Huang ,  Lei Shi ,  Yueh-Se Ho

发明人： Tao Feng ,  Zhiqiang Niu ,  Yuping Gong ,  Ruisheng Wu ,  Ping Huang ,  Lei Shi ,  Yueh-Se Ho

IPC分类号： H01L23/495 ,  H01L23/498

CPC分类号： H01L21/6836 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76897 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/495 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/73 ,  H01L24/94 ,  H01L25/50 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/051 ,  H01L2224/05139 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/0616 ,  H01L2224/06181 ,  H01L2224/1184 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.

摘要翻译： 无基底复合功率半导体器件可以包括薄衬底和位于衬底顶表面上的顶金属层。 衬底和外延层的总厚度可以小于25微米。 焊料凸块形成在顶部金属层的顶部，并且模塑料围绕焊料凸起并且使焊料凸块至少部分暴露。

公开(公告)号：US09391005B2

公开(公告)日：2016-07-12

申请号：US14033140

申请日：2013-09-20

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC分类号： H01L23/495

CPC分类号： H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/16245 ,  H01L2924/13091 ,  H01L2924/00

摘要： A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

摘要翻译： 功率半导体封装具有超薄芯片，具有正面成型以降低基板电阻; 具有位于两侧引线上的凹槽的引线框单元提供精确的定位，用于将多个桥形金属夹连接到侧引线的前侧。 桥形金属夹具有桥结构和半或完全蚀刻的通孔，用于在制造过程中缓解多余的焊料。