公开(公告)号：US06566239B2

公开(公告)日：2003-05-20

申请号：US09867545

申请日：2001-05-31

申请人： Yutaka Makino ,  Eiji Watanabe ,  Hirohisa Matsuki ,  Tetsuya Fujisawa

发明人： Yutaka Makino ,  Eiji Watanabe ,  Hirohisa Matsuki ,  Tetsuya Fujisawa

IPC分类号： H01L2144

CPC分类号： H01L21/288 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00014

摘要： A method of manufacturing a semiconductor device is provided. The method includes the steps of forming a wiring layer on an underlying metal film formed on a substrate, the wiring layer being electrically connected to an electrode pad formed on a substrate, removing a part of the wiring layer so as to form a wiring on the substrate, a part of the underlying metal film being exposed other than a part where the wiring is formed, removing the exposed part of the underlying metal film by using the wiring as a mask, forming a barrier metal film on the wiring so as to cover the wiring and the underlying metal film underneath the wiring, forming a post terminal by electroless plating so that the post terminal is electrically connected to said wiring and providing a sealing resin so as to cover said substrate except a position at which said post terminal is formed.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括以下步骤：在形成在基板上的下面的金属膜上形成布线层，该布线层与形成在基板上的电极焊盘电连接，去除一部分布线层，以形成布线层 基板，除了形成布线的部分之外，一部分下面的金属膜被露出，通过使用布线作为掩模去除下面的金属膜的暴露部分，在布线上形成阻挡金属膜以覆盖 布线和下面的金属膜，通过无电镀形成后端子，使得端子端子与所述布线电连接并提供密封树脂，以便覆盖所述基板，除了形成所述柱端子的位置 。

公开(公告)号：US06548898B2

公开(公告)日：2003-04-15

申请号：US09895330

申请日：2001-07-02

申请人： Hirohisa Matsuki ,  Yutaka Makino ,  Masamitsu Ikumo ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshitaka Aiba

发明人： Hirohisa Matsuki ,  Yutaka Makino ,  Masamitsu Ikumo ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshitaka Aiba

IPC分类号： H01L2352

CPC分类号： H01L24/05 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/02126 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/1358 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/814 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K3/244 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

摘要翻译： 其中磷镍层，含有比该磷 - 镍层高的​​磷或硼的富磷镍层，镍锡合金层，富锡锡合金层和锡合金焊料层的结构是 在电极上依次形成。 因此，可以提高用作电极的金属图案，布线或焊盘和焊料之间的粘合性。

公开(公告)号：US06784543B2

公开(公告)日：2004-08-31

申请号：US10374965

申请日：2003-02-28

申请人： Hirohisa Matsuki ,  Yutaka Makino ,  Masamitsu Ikumo ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshitaka Aiba

发明人： Hirohisa Matsuki ,  Yutaka Makino ,  Masamitsu Ikumo ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshitaka Aiba

IPC分类号： H01L2352

CPC分类号： H01L24/05 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/02126 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/1358 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/814 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K3/244 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

摘要翻译： 其中磷镍层，含有比该磷 - 镍层高的​​磷或硼的富磷镍层，镍锡合金层，富锡锡合金层和锡合金焊料层的结构是 在电极上依次形成。 因此，可以提高用作电极的金属图案，布线或焊盘和焊料之间的粘合性。

公开(公告)号：US06218281B1

公开(公告)日：2001-04-17

申请号：US09192443

申请日：1998-11-16

申请人： Eiji Watanabe ,  Hirohisa Matsuki ,  Kenichi Kado ,  Kenichi Nagashige ,  Masanori Onodera ,  Kunio Kodama ,  Hiroyuki Yoda ,  Joji Fujimori ,  Minoru Nakada ,  Yutaka Makino

发明人： Eiji Watanabe ,  Hirohisa Matsuki ,  Kenichi Kado ,  Kenichi Nagashige ,  Masanori Onodera ,  Kunio Kodama ,  Hiroyuki Yoda ,  Joji Fujimori ,  Minoru Nakada ,  Yutaka Makino

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02377 ,  H01L2224/03462 ,  H01L2224/039 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81805

摘要： A semiconductor substrate is prepared which has a principal surface, an exposed pad made of conductive material being formed in a partial area of the principal surface, and the other area of the principal surface being covered with a first insulating film. A base conductive film is formed on the first insulating film and the pad. A photoresist film having a thickness of 50 &mgr;m or thicker is formed on the base conductive film. An opening is formed through the photoresist film in an area corresponding to the pad to expose a partial surface area of the base conductive film. A conductive bump electrode is deposited on the base conductive film exposed on a bottom of the opening. The photoresist film is removed. This method is suitable for making a fine pitch between bump electrodes.

摘要翻译： 制备半导体衬底，其具有主表面，由导电材料制成的裸露焊盘形成在主表面的局部区域中，并且主表面的另一区域被第一绝缘膜覆盖。 在第一绝缘膜和垫上形成基底导电膜。 在基底导电膜上形成厚度为50μm以上的光刻胶膜。 在与该焊盘相对应的区域中形成通过光致抗蚀剂膜的开口以暴露基底导电膜的部分表面区域。 导电凸块电极沉积在暴露在开口底部的基底导电膜上。 除去光致抗蚀剂膜。 该方法适用于在凸块电极之间形成细间距。

公开(公告)号：US06836025B2

公开(公告)日：2004-12-28

申请号：US10448444

申请日：2003-05-30

申请人： Tetsuya Fujisawa ,  Hirohisa Matsuki ,  Osamu Igawa ,  Yoshitaka Aiba ,  Masamitsu Ikumo ,  Mitsutaka Sato

发明人： Tetsuya Fujisawa ,  Hirohisa Matsuki ,  Osamu Igawa ,  Yoshitaka Aiba ,  Masamitsu Ikumo ,  Mitsutaka Sato

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24155 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/24265 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/48471 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a semiconductor device circuit formation surfaces of each of a plurality of semiconductor chips can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified. The semiconductor chips are mounted on a substrate via an adhesive layer in a two-dimensional arrangement. A resin layer is formed on the substrate and located around the semiconductor elements. The resin layer has the same thickness as a thickness of the semiconductor elements. An organic insulating layer is formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements. A rearrangement wiring layer is formed on the organic insulating layer and electrodes of the semiconductor chips. External connection terminals are electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.

摘要翻译： 在半导体器件中，当半导体芯片并排布置时，多个半导体芯片中的每一个的形成表面可以容易地位于均匀的水平，从而简化了布置布线的处理。 半导体芯片通过二维布置的粘合剂层安装在基板上。 树脂层形成在基板上并位于半导体元件周围。 树脂层的厚度与半导体元件的厚度相同。 在树脂层的表面和半导体元件的电路形成表面上形成有机绝缘层。 在有机绝缘层和半导体芯片的电极上形成重排布线层。 外部连接端子通过布线布线层中的布线电连接到半导体元件的电路形成表面。

公开(公告)号：US06696754B2

公开(公告)日：2004-02-24

申请号：US10214306

申请日：2002-08-08

申请人： Mitsutaka Sato ,  Tetsuya Fujisawa ,  Shigeyuki Maruyama ,  Junichi Kasai ,  Toshimi Kawahara ,  Toshio Hamano ,  Yoshihiro Kubota ,  Mitsunada Osawa ,  Yoshiyuki Yoneda ,  Kazuto Tsuji ,  Hirohisa Matsuki

发明人： Mitsutaka Sato ,  Tetsuya Fujisawa ,  Shigeyuki Maruyama ,  Junichi Kasai ,  Toshimi Kawahara ,  Toshio Hamano ,  Yoshihiro Kubota ,  Mitsunada Osawa ,  Yoshiyuki Yoneda ,  Kazuto Tsuji ,  Hirohisa Matsuki

IPC分类号： H01L2334

CPC分类号： H01L25/105 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2924/09701 ,  H01L2924/1533 ,  H01L2924/3025 ,  H01R12/82 ,  H05K7/1431 ,  H01L2924/00

摘要： A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.

摘要翻译： 半导体模块包括多个半导体器件，每个半导体器件包括承载有单个存储器半导体芯片的电路衬底和用于可拆卸地保持半导体器件的插座。

公开(公告)号：US06472744B2

公开(公告)日：2002-10-29

申请号：US09084097

申请日：1998-05-26

申请人： Mitsutaka Sato ,  Tetsuya Fujisawa ,  Shigeyuki Maruyama ,  Junichi Kasai ,  Toshimi Kawahara ,  Toshio Hamano ,  Yoshihiro Kubota ,  Mitsunada Osawa ,  Yoshiyuki Yoneda ,  Kazuto Tsuji ,  Hirohisa Matsuki

发明人： Mitsutaka Sato ,  Tetsuya Fujisawa ,  Shigeyuki Maruyama ,  Junichi Kasai ,  Toshimi Kawahara ,  Toshio Hamano ,  Yoshihiro Kubota ,  Mitsunada Osawa ,  Yoshiyuki Yoneda ,  Kazuto Tsuji ,  Hirohisa Matsuki

IPC分类号： H01L2500

CPC分类号： H01L25/105 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2924/09701 ,  H01L2924/1533 ,  H01L2924/3025 ,  H01R12/82 ,  H05K7/1431 ,  H01L2924/00

摘要： A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.

摘要翻译： 半导体模块包括多个半导体器件，每个半导体器件包括承载有单个存储器半导体芯片的电路衬底和用于可分离地保持半导体器件的插座。

公开(公告)号：US06344407B1

公开(公告)日：2002-02-05

申请号：US09691075

申请日：2000-10-19

申请人： Hirohisa Matsuki ,  Fumihiko Taniguchi ,  Kunio Kodama ,  Eiji Watanabe ,  Masataka Mizukoshi ,  Hiroyuki Matsui

发明人： Hirohisa Matsuki ,  Fumihiko Taniguchi ,  Kunio Kodama ,  Eiji Watanabe ,  Masataka Mizukoshi ,  Hiroyuki Matsui

IPC分类号： B23K3522

CPC分类号： B23K35/38 ,  B23K35/262 ,  B23K35/268 ,  B23K35/3618 ,  B23K2101/40 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01054 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15787 ,  H05K3/3489 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05166

摘要： A semiconductor device manufacturing method comprises the steps of forming solder bumps on an underlying metal film of a semiconductor device, and placing the semiconductor device and the solder layer in a reduced pressure atmosphere containing formic acid to form the solder bumps. Accordingly, the solder bumps can be formed without flux generating voids in the solder layer. Furthermore, the cleaning required after the solder bumps are formed can be omitted.

摘要翻译： 半导体器件制造方法包括以下步骤：在半导体器件的下面的金属膜上形成焊料凸块，并将半导体器件和焊料层放置在含有甲酸的减压气氛中以形成焊料凸块。 因此，可以在焊料层中形成焊剂凸块而没有焊剂产生空隙。 此外，可以省略在形成焊料凸块之后所需的清洁。

公开(公告)号：US06232147B1

公开(公告)日：2001-05-15

申请号：US09365413

申请日：1999-08-02

申请人： Hirohisa Matsuki ,  Kenichi Kado ,  Eiji Watanabe ,  Kazuyuki Imamura ,  Takahiro Yurino

发明人： Hirohisa Matsuki ,  Kenichi Kado ,  Eiji Watanabe ,  Kazuyuki Imamura ,  Takahiro Yurino

IPC分类号： H01L2144

CPC分类号： H01L24/10 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/013

摘要： A semiconductor device equipped with secondary pads having adequate arrangement for an arbitrary packaging process. The secondary pads are connected with the primary pads of the semiconductor device with a novel lead wire structure, which is characterized by its low electric resistance, good mechanical strength to protect active components of the device, good adhesion to bumps, and anti-electromigration property. The semiconductor device has: semiconductor circuit elements 2 embedded in a semiconductor substrate 1; a plurality of conductive primary pads 4 each formed in a region above, and surrounding, the circuit element 2; a first protective insulation substrate 5 covering the substrate and having first openings 6 for the primary pads 4; lead wires 7 each consisting of a conductive bulk layer 15 made of copper and a metallic top layer 16, the bulk layer formed on the first protective insulation substrate 5 and having one end connected with a corresponding one of the primary pads 4 through an associated opening 6 and the other end located in a region surrounding the opening 6, while the top layer made of a metal having Vickers hardness of more than 100; and a second protective insulation substrate 8 having second openings 9 for exposing the top surfaces of the other ends of the lead wires 7 serving as the secondary pads 17.

摘要翻译： 一种装备有用于任意包装过程的适当布置的辅助垫的半导体器件。 辅助焊盘与半导体器件的主焊盘与新颖的引线结构连接，其特征在于其低电阻，良好的机械强度以保护器件的有源部件，对凸块的良好粘附性和抗电迁移性 。 半导体器件具有：嵌入半导体衬底1中的半导体电路元件2; 多个导电性主焊盘4，各自形成在电路元件2的上方并包围电路元件2的区域中; 覆盖基板并具有用于主焊盘4的第一开口6的第一保护绝缘基板5; 引线7由导电体层15和铜构成，金属顶层16形成在第一保护绝缘基片5上，并且其一端通过相关的开口连接到相应的一个主焊盘4中 6，另一端位于围绕开口6的区域中，而顶层由维氏硬度大于100的金属制成; 以及具有第二开口9的第二保护绝缘基板8，用于暴露作为二次焊盘17的引线7的另一端的顶表面。

公开(公告)号：US5969424A

公开(公告)日：1999-10-19

申请号：US999115

申请日：1997-12-29

申请人： Hirohisa Matsuki ,  Kenichi Kado ,  Eiji Watanabe ,  Kazuyuki Imamura ,  Takahiro Yurino

发明人： Hirohisa Matsuki ,  Kenichi Kado ,  Eiji Watanabe ,  Kazuyuki Imamura ,  Takahiro Yurino

IPC分类号： H01L23/485 ,  H01L23/498 ,  H01L23/48

CPC分类号： H01L24/10 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181

摘要： A semiconductor device equipped with secondary pads having adequate arrangement for an arbitrary packaging process. The secondary pads are connected with the primary pads of the semiconductor device with a novel lead wire structure, which is characterized by its low electric resistance, good mechanical strength to protect active components of the device, good adhesion to bumps, and anti-electromigration property. The semiconductor device has: semiconductor circuit elements 2 embedded in a semiconductor substrate 1; a plurality of conductive primary pads 4 each formed in a region above, and surrounding, the circuit element 2; a first protective insulation substrate 5 covering the substrate and having first openings 6 for the primary pads 4; lead wires 7 each consisting of a conductive bulk layer 15 made of copper and a metallic top layer 16, the bulk layer formed on the first protective insulation substrate 5 and having one end connected with a corresponding one of the primary pads 4 through an associated opening 6 and the other end located in a region surrounding the opening 6, while the top layer made of a metal having Vickers hardness of more than 100; and a second protective insulation substrate 8 having second openings 9 for exposing the top surfaces of the other ends of the lead wires 7 serving as the secondary pads 17.

摘要翻译： 一种装备有用于任意包装过程的适当布置的辅助垫的半导体器件。 辅助焊盘与半导体器件的主焊盘与新颖的引线结构连接，其特征在于其低电阻，良好的机械强度以保护器件的有源部件，对凸块的良好粘附性和抗电迁移性 。 半导体器件具有：嵌入半导体衬底1中的半导体电路元件2; 多个导电性主焊盘4，各自形成在电路元件2的上方并包围电路元件2的区域中; 覆盖基板并具有用于主焊盘4的第一开口6的第一保护绝缘基板5; 引线7由导电体层15和铜构成，金属顶层16形成在第一保护绝缘基片5上，并且其一端通过相关的开口连接到相应的一个主焊盘4中 6，另一端位于围绕开口6的区域中，而顶层由维氏硬度大于100的金属制成; 以及具有第二开口9的第二保护绝缘基板8，用于暴露作为二次焊盘17的引线7的另一端的顶表面。