公开(公告)号：US06218281B1

公开(公告)日：2001-04-17

申请号：US09192443

申请日：1998-11-16

申请人： Eiji Watanabe ,  Hirohisa Matsuki ,  Kenichi Kado ,  Kenichi Nagashige ,  Masanori Onodera ,  Kunio Kodama ,  Hiroyuki Yoda ,  Joji Fujimori ,  Minoru Nakada ,  Yutaka Makino

发明人： Eiji Watanabe ,  Hirohisa Matsuki ,  Kenichi Kado ,  Kenichi Nagashige ,  Masanori Onodera ,  Kunio Kodama ,  Hiroyuki Yoda ,  Joji Fujimori ,  Minoru Nakada ,  Yutaka Makino

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02377 ,  H01L2224/03462 ,  H01L2224/039 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81805

摘要： A semiconductor substrate is prepared which has a principal surface, an exposed pad made of conductive material being formed in a partial area of the principal surface, and the other area of the principal surface being covered with a first insulating film. A base conductive film is formed on the first insulating film and the pad. A photoresist film having a thickness of 50 &mgr;m or thicker is formed on the base conductive film. An opening is formed through the photoresist film in an area corresponding to the pad to expose a partial surface area of the base conductive film. A conductive bump electrode is deposited on the base conductive film exposed on a bottom of the opening. The photoresist film is removed. This method is suitable for making a fine pitch between bump electrodes.

摘要翻译： 制备半导体衬底，其具有主表面，由导电材料制成的裸露焊盘形成在主表面的局部区域中，并且主表面的另一区域被第一绝缘膜覆盖。 在第一绝缘膜和垫上形成基底导电膜。 在基底导电膜上形成厚度为50μm以上的光刻胶膜。 在与该焊盘相对应的区域中形成通过光致抗蚀剂膜的开口以暴露基底导电膜的部分表面区域。 导电凸块电极沉积在暴露在开口底部的基底导电膜上。 除去光致抗蚀剂膜。 该方法适用于在凸块电极之间形成细间距。

公开(公告)号：US06232147B1

公开(公告)日：2001-05-15

申请号：US09365413

申请日：1999-08-02

申请人： Hirohisa Matsuki ,  Kenichi Kado ,  Eiji Watanabe ,  Kazuyuki Imamura ,  Takahiro Yurino

发明人： Hirohisa Matsuki ,  Kenichi Kado ,  Eiji Watanabe ,  Kazuyuki Imamura ,  Takahiro Yurino

IPC分类号： H01L2144

CPC分类号： H01L24/10 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/013

摘要： A semiconductor device equipped with secondary pads having adequate arrangement for an arbitrary packaging process. The secondary pads are connected with the primary pads of the semiconductor device with a novel lead wire structure, which is characterized by its low electric resistance, good mechanical strength to protect active components of the device, good adhesion to bumps, and anti-electromigration property. The semiconductor device has: semiconductor circuit elements 2 embedded in a semiconductor substrate 1; a plurality of conductive primary pads 4 each formed in a region above, and surrounding, the circuit element 2; a first protective insulation substrate 5 covering the substrate and having first openings 6 for the primary pads 4; lead wires 7 each consisting of a conductive bulk layer 15 made of copper and a metallic top layer 16, the bulk layer formed on the first protective insulation substrate 5 and having one end connected with a corresponding one of the primary pads 4 through an associated opening 6 and the other end located in a region surrounding the opening 6, while the top layer made of a metal having Vickers hardness of more than 100; and a second protective insulation substrate 8 having second openings 9 for exposing the top surfaces of the other ends of the lead wires 7 serving as the secondary pads 17.

摘要翻译： 一种装备有用于任意包装过程的适当布置的辅助垫的半导体器件。 辅助焊盘与半导体器件的主焊盘与新颖的引线结构连接，其特征在于其低电阻，良好的机械强度以保护器件的有源部件，对凸块的良好粘附性和抗电迁移性 。 半导体器件具有：嵌入半导体衬底1中的半导体电路元件2; 多个导电性主焊盘4，各自形成在电路元件2的上方并包围电路元件2的区域中; 覆盖基板并具有用于主焊盘4的第一开口6的第一保护绝缘基板5; 引线7由导电体层15和铜构成，金属顶层16形成在第一保护绝缘基片5上，并且其一端通过相关的开口连接到相应的一个主焊盘4中 6，另一端位于围绕开口6的区域中，而顶层由维氏硬度大于100的金属制成; 以及具有第二开口9的第二保护绝缘基板8，用于暴露作为二次焊盘17的引线7的另一端的顶表面。

公开(公告)号：US5969424A

公开(公告)日：1999-10-19

申请号：US999115

申请日：1997-12-29

申请人： Hirohisa Matsuki ,  Kenichi Kado ,  Eiji Watanabe ,  Kazuyuki Imamura ,  Takahiro Yurino

发明人： Hirohisa Matsuki ,  Kenichi Kado ,  Eiji Watanabe ,  Kazuyuki Imamura ,  Takahiro Yurino

IPC分类号： H01L23/485 ,  H01L23/498 ,  H01L23/48

CPC分类号： H01L24/10 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181

摘要： A semiconductor device equipped with secondary pads having adequate arrangement for an arbitrary packaging process. The secondary pads are connected with the primary pads of the semiconductor device with a novel lead wire structure, which is characterized by its low electric resistance, good mechanical strength to protect active components of the device, good adhesion to bumps, and anti-electromigration property. The semiconductor device has: semiconductor circuit elements 2 embedded in a semiconductor substrate 1; a plurality of conductive primary pads 4 each formed in a region above, and surrounding, the circuit element 2; a first protective insulation substrate 5 covering the substrate and having first openings 6 for the primary pads 4; lead wires 7 each consisting of a conductive bulk layer 15 made of copper and a metallic top layer 16, the bulk layer formed on the first protective insulation substrate 5 and having one end connected with a corresponding one of the primary pads 4 through an associated opening 6 and the other end located in a region surrounding the opening 6, while the top layer made of a metal having Vickers hardness of more than 100; and a second protective insulation substrate 8 having second openings 9 for exposing the top surfaces of the other ends of the lead wires 7 serving as the secondary pads 17.

摘要翻译： 一种装备有用于任意包装过程的适当布置的辅助垫的半导体器件。 辅助焊盘与半导体器件的主焊盘与新颖的引线结构连接，其特征在于其低电阻，良好的机械强度以保护器件的有源部件，对凸块的良好粘附性和抗电迁移性 。 半导体器件具有：嵌入半导体衬底1中的半导体电路元件2; 多个导电性主焊盘4，各自形成在电路元件2的上方并包围电路元件2的区域中; 覆盖基板并具有用于主焊盘4的第一开口6的第一保护绝缘基板5; 引线7由导电体层15和铜构成，金属顶层16形成在第一保护绝缘基片5上，并且其一端通过相关的开口连接到相应的一个主焊盘4中 6，另一端位于围绕开口6的区域中，而顶层由维氏硬度大于100的金属制成; 以及具有第二开口9的第二保护绝缘基板8，用于暴露作为二次焊盘17的引线7的另一端的顶表面。

公开(公告)号：US06344407B1

公开(公告)日：2002-02-05

申请号：US09691075

申请日：2000-10-19

申请人： Hirohisa Matsuki ,  Fumihiko Taniguchi ,  Kunio Kodama ,  Eiji Watanabe ,  Masataka Mizukoshi ,  Hiroyuki Matsui

发明人： Hirohisa Matsuki ,  Fumihiko Taniguchi ,  Kunio Kodama ,  Eiji Watanabe ,  Masataka Mizukoshi ,  Hiroyuki Matsui

IPC分类号： B23K3522

CPC分类号： B23K35/38 ,  B23K35/262 ,  B23K35/268 ,  B23K35/3618 ,  B23K2101/40 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01054 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15787 ,  H05K3/3489 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05166

摘要： A semiconductor device manufacturing method comprises the steps of forming solder bumps on an underlying metal film of a semiconductor device, and placing the semiconductor device and the solder layer in a reduced pressure atmosphere containing formic acid to form the solder bumps. Accordingly, the solder bumps can be formed without flux generating voids in the solder layer. Furthermore, the cleaning required after the solder bumps are formed can be omitted.

摘要翻译： 半导体器件制造方法包括以下步骤：在半导体器件的下面的金属膜上形成焊料凸块，并将半导体器件和焊料层放置在含有甲酸的减压气氛中以形成焊料凸块。 因此，可以在焊料层中形成焊剂凸块而没有焊剂产生空隙。 此外，可以省略在形成焊料凸块之后所需的清洁。

公开(公告)号：US06566239B2

公开(公告)日：2003-05-20

申请号：US09867545

申请日：2001-05-31

申请人： Yutaka Makino ,  Eiji Watanabe ,  Hirohisa Matsuki ,  Tetsuya Fujisawa

发明人： Yutaka Makino ,  Eiji Watanabe ,  Hirohisa Matsuki ,  Tetsuya Fujisawa

IPC分类号： H01L2144

CPC分类号： H01L21/288 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00014

摘要： A method of manufacturing a semiconductor device is provided. The method includes the steps of forming a wiring layer on an underlying metal film formed on a substrate, the wiring layer being electrically connected to an electrode pad formed on a substrate, removing a part of the wiring layer so as to form a wiring on the substrate, a part of the underlying metal film being exposed other than a part where the wiring is formed, removing the exposed part of the underlying metal film by using the wiring as a mask, forming a barrier metal film on the wiring so as to cover the wiring and the underlying metal film underneath the wiring, forming a post terminal by electroless plating so that the post terminal is electrically connected to said wiring and providing a sealing resin so as to cover said substrate except a position at which said post terminal is formed.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括以下步骤：在形成在基板上的下面的金属膜上形成布线层，该布线层与形成在基板上的电极焊盘电连接，去除一部分布线层，以形成布线层 基板，除了形成布线的部分之外，一部分下面的金属膜被露出，通过使用布线作为掩模去除下面的金属膜的暴露部分，在布线上形成阻挡金属膜以覆盖 布线和下面的金属膜，通过无电镀形成后端子，使得端子端子与所述布线电连接并提供密封树脂，以便覆盖所述基板，除了形成所述柱端子的位置 。

公开(公告)号：US06732911B2

公开(公告)日：2004-05-11

申请号：US09970802

申请日：2001-10-05

申请人： Hirohisa Matsuki ,  Hiroyuki Matsui ,  Eiji Yoshida ,  Takao Ohno ,  Koki Otake ,  Akiyo Mizutani ,  Motoshu Miyajima ,  Masataka Mizukoshi ,  Eiji Watanabe

发明人： Hirohisa Matsuki ,  Hiroyuki Matsui ,  Eiji Yoshida ,  Takao Ohno ,  Koki Otake ,  Akiyo Mizutani ,  Motoshu Miyajima ,  Masataka Mizukoshi ,  Eiji Watanabe

IPC分类号： B23K3538

CPC分类号： B23K1/008 ,  B23K2101/36 ,  H05K3/3489

摘要： There is provided a chamber open to the outside through openings through which a solder-adhered object is passed and the chamber having a heating/melting area, a carrying mechanism for carrying the solder-adhered object into the heating/melting area, a formic-acid supplying means for supplying a formic acid into the heating/melting area, an exhausting means for exhausting a gas from the heating/melting area and its neighboring area to create a lower pressure area in the heating/melting area as compared to the pressure of outside the chamber, heating means for heating directly or indirectly the solder-adhered object in the heating/melting area, and an air-stream suppressing means for disturbing a gas flow between the heating/melting area and the carrying areas. Accordingly, there can be provided a solder jointing system for jointing solder layers of a semiconductor device, an electronic device, or the like to the wirings or the pads, which is capable of having a high processing ability and preventing re-oxidation.

摘要翻译： 设置有通过开口穿过焊料粘附物体的开口的室，并且具有加热/熔化区域的室，用于将焊料粘附物携带到加热/熔融区域中的承载机构， 用于将甲酸供应到加热/熔化区域的酸供应装置，用于从加热/熔化区域及其相邻区域排出气体的排气装置，以在加热/熔化区域中产生较低压力区域， 在室外，用于在加热/熔化区域中直接或间接加热焊接物体的加热装置，以及用于扰乱加热/熔化区域和承载区域之间的气流的气流抑制装置。 因此，可以提供一种用于将半导体器件，电子器件等的焊料层接合到布线或焊盘上的焊接接合系统，其能够具有高处理能力并防止再氧化。

公开(公告)号：US5656550A

公开(公告)日：1997-08-12

申请号：US611007

申请日：1996-03-05

申请人： Kazuto Tsuji ,  Yoshiyuki Yoneda ,  Hideharu Sakoda ,  Ryuji Nomoto ,  Eiji Watanabe ,  Seiichi Orimo ,  Masanori Onodera ,  Masaki Waki

发明人： Kazuto Tsuji ,  Yoshiyuki Yoneda ,  Hideharu Sakoda ,  Ryuji Nomoto ,  Eiji Watanabe ,  Seiichi Orimo ,  Masanori Onodera ,  Masaki Waki

IPC分类号： H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495 ,  H01L21/60

CPC分类号： H01L24/49 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49548 ,  H01L23/49551 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3011 ,  Y10T29/49121

摘要： This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion. Also, the semiconductor device has a semiconductor chip having a predetermined number of electrode pads, a predetermined number of leads electrically connected to the electrode pads, each of the leads having a projecting terminal portion formed by bending the lead, and a resin portion sealing the semiconductor chip and the leads, wherein the terminal portions are exposed from one face of the resin portion.

摘要翻译： 本发明涉及一种半导体器件，其中多个外部端子以平坦表面的格子状排列。 半导体器件具有半导体芯片，具有引线部分的引线部分和与引线部分整体连接的外部连接端子，引线部分电连接到半导体芯片，引线部分从半导体芯片向外延伸，外部连接 从所述引线部分向下延伸的端子，密封所述半导体芯片和所述引线部分的密封树脂，所述半导体芯片的底面和所述引线部分的底面从所述密封树脂露出;以及绝缘构件， 和半导体芯片的底面。 此外，半导体器件具有预定数量的电极焊盘的半导体芯片，与电极焊盘电连接的预定数量的引线，每个引线具有通过弯曲引线形成的突出端子部分和密封 半导体芯片和引线，其中端子部分从树脂部分的一个面露出。

公开(公告)号：US6025650A

公开(公告)日：2000-02-15

申请号：US961243

申请日：1997-10-30

申请人： Kazuto Tsuji ,  Yoshiyuki Yoneda ,  Hideharu Sakoda ,  Ryuuji Nomoto ,  Eiji Watanabe ,  Seiichi Orimo ,  Masanori Onodera ,  Junichi Kasai

发明人： Kazuto Tsuji ,  Yoshiyuki Yoneda ,  Hideharu Sakoda ,  Ryuuji Nomoto ,  Eiji Watanabe ,  Seiichi Orimo ,  Masanori Onodera ,  Junichi Kasai

IPC分类号： H01L23/12 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495 ,  H01L23/48 ,  H01L29/41

CPC分类号： H01L21/6835 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49548 ,  H01L24/49 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165

摘要： This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device comprises a semiconductor chip having a plurality of pads, a resin portion sealing said semiconductor chip and a terminal portion in which a prescribed number of pole terminals electrically connected to said pads provided in said semiconductor chip are provided, said pole terminals being exposed from said resin portion. According to the invention, a cost for production is reduced and a reliability and electrical characteristics can be improved.

摘要翻译： 本发明涉及一种半导体器件，其中多个外部端子以平坦表面的格子状排列。 半导体器件包括具有多个焊盘的半导体芯片，密封所述半导体芯片的树脂部分和设置有电连接到设置在所述半导体芯片中的所述焊盘的规定数量的极端子的端子部分，所述极端子露出 从所述树脂部分。 根据本发明，生产成本降低，并且可以提高可靠性和电气特性。

公开(公告)号：US06255740B1

公开(公告)日：2001-07-03

申请号：US08847222

申请日：1997-05-01

申请人： Kazuto Tsuji ,  Yoshiyuki Yoneda ,  Hideharu Sakoda ,  Ryuji Nomoto ,  Eiji Watanabe ,  Seiichi Orimo ,  Masanori Onodera ,  Masaki Waki

发明人： Kazuto Tsuji ,  Yoshiyuki Yoneda ,  Hideharu Sakoda ,  Ryuji Nomoto ,  Eiji Watanabe ,  Seiichi Orimo ,  Masanori Onodera ,  Masaki Waki

IPC分类号： H01L2329

CPC分类号： H01L24/49 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49548 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3011 ,  Y10T29/49121 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

摘要： This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion. Also, the semiconductor device has a semiconductor chip having a predetermined number of electrode pads, a predetermined number of leads electrically connected to the electrode pads, each of the leads having a projecting terminal portion formed by bending the lead, and a resin portion sealing the semiconductor chip and the leads, wherein the terminal portions are exposed from one face of the resin portion.

摘要翻译： 本发明涉及一种半导体器件，其中多个外部端子以平坦表面的格子状排列。 半导体器件具有半导体芯片，具有引线部分的引线部分和与引线部分整体连接的外部连接端子，引线部分电连接到半导体芯片，引线部分从半导体芯片向外延伸，外部连接 从所述引线部分向下延伸的端子，密封所述半导体芯片和所述引线部分的密封树脂，所述半导体芯片的底面和所述引线部分的底面从所述密封树脂露出;以及绝缘构件， 和半导体芯片的底面。 此外，半导体器件具有预定数量的电极焊盘的半导体芯片，与电极焊盘电连接的预定数量的引线，每个引线具有通过弯曲引线形成的突出端子部分和密封 半导体芯片和引线，其中端子部分从树脂部分的一个面露出。

公开(公告)号：US08420522B2

公开(公告)日：2013-04-16

申请号：US12213819

申请日：2008-06-25

申请人： Masamitsu Ikumo ,  Hiroyuki Yoda ,  Eiji Watanabe

发明人： Masamitsu Ikumo ,  Hiroyuki Yoda ,  Eiji Watanabe

IPC分类号： H01L21/44

CPC分类号： H01L24/12 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0381 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/1132 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/131 ,  H01L2224/73253 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2224/13099 ,  H01L2924/00014

摘要： A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas of the electrode layers. Thickness of the organic insulation film situated in the vicinity of the periphery of the projection electrodes is greater than thickness of the organic insulation film situated between the projection electrodes.

摘要翻译： 半导体器件包括设置在半导体衬底的指定位置处的多个电极层，通过选择性地暴露电极层的指定区域和用于外部连接的突出电极而形成在半导体衬底上的有机绝缘膜，所述突起电极形成在 电极层的指定区域。 位于突出电极周围附近的有机绝缘膜的厚度大于位于突出电极之间的有机绝缘膜的厚度。