公开(公告)号：US20150189763A1

公开(公告)日：2015-07-02

申请号：US14412594

申请日：2013-06-25

申请人： AT&S Austria Technologie & Systemtechnik Aktiengesellschaft

发明人： Wolfgang Schrittwieser

IPC分类号： H05K3/30 ,  H05K3/20 ,  H05K3/08 ,  H05K1/18

CPC分类号： H05K3/305 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82132 ,  H01L2224/83129 ,  H01L2224/83132 ,  H01L2224/92244 ,  H01L2924/12042 ,  H05K1/186 ,  H05K1/188 ,  H05K3/0008 ,  H05K3/08 ,  H05K3/202 ,  Y10T29/49133 ,  H01L2924/00

摘要： The invention relates to a method for embedding at least one component in a printed circuit board, comprising the steps of providing a lower metal conductor foil applied to a first metal supporting layer, forming recessed alignment marks in the conductor foil, applying an adhesive layer in a registered manner in relation to the alignment marks and fitting a component via the rear face thereof on the adhesive layer with upwardly pointing connection areas, curing the adhesive layer, embedding the component in an insulting layer, applying a metal upper conductor foil and an upper metal supporting layer, consolidating the structure, removing the supporting layers, exposing the alignment marks of the lower conductor foil by removing the insulating layer, producing cutouts ending at the lower conductor foil, producing bores to the connection areas of the component in a registered manner in relation to the alignment marks, and applying a conductor layer to the upper face of the structure, producing contact connections in the bores to the connection areas of the component, and structuring the conductor layer in order to produce conductive tracks.

摘要翻译： 本发明涉及一种在印刷电路板中嵌入至少一个部件的方法，包括以下步骤：提供施加到第一金属支撑层的下金属导体箔，在导体箔中形成凹入的对准标记，将粘合剂层 相对于对准标记注册的方式，并且通过其后表面将部件装配在粘合剂层上，具有向上指向的连接区域，固化粘合剂层，将部件包埋在绝缘层中，施加金属上导体箔和上部 金属支撑层，固结结构，去除支撑层，通过去除绝缘层露出下导体箔的对准标记，产生以下导体箔终止的切口，以注册方式向组件的连接区域产生孔 相对于对准标记，并且将导体层施加到结构的上表面 将孔中的接触连接连接到部件的连接区域，并且构造导体层以便产生导电轨道。

公开(公告)号：US09666516B2

公开(公告)日：2017-05-30

申请号：US14556258

申请日：2014-12-01

申请人： General Electric Company

发明人： Scott Smith ,  Christopher James Kapusta ,  Glenn Alan Forman ,  Eric Patrick Davis

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48 ,  H01L21/288 ,  H01L21/66

CPC分类号： H01L23/49827 ,  H01L21/2885 ,  H01L21/486 ,  H01L22/12 ,  H01L22/14 ,  H01L22/22 ,  H01L23/49838 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82106 ,  H01L2224/82138 ,  H01L2224/83129 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/82

摘要： An electronic package and a method of making the same in provided. The electronic package includes a dielectric layer and a conformal masking layer disposed on at least a portion of the dielectric layer. The electronic package further includes a routing layer disposed on at least a portion of the masking layer and a micro-via disposed at least in part in the conformal masking layer and the routing layer. Further, at least a portion of the routing layer forms a conformal electrically conductive layer in at least a portion of the micro-via. Also, the conformal masking layer is configured to define a size of the micro-via. The electronic package further includes a semiconductor die operatively coupled to the micro-via.

公开(公告)号：US20160155693A1

公开(公告)日：2016-06-02

申请号：US14556258

申请日：2014-12-01

申请人： General Electric Company

发明人： Scott Smith ,  Christopher James Kapusta ,  Glenn Alan Forman ,  Eric Patrick Davis

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/288 ,  H01L25/065 ,  H01L21/48

CPC分类号： H01L23/49827 ,  H01L21/2885 ,  H01L21/486 ,  H01L22/12 ,  H01L22/14 ,  H01L22/22 ,  H01L23/49838 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82106 ,  H01L2224/82138 ,  H01L2224/83129 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/82

摘要： An electronic package and a method of making the same in provided. The electronic package includes a dielectric layer and a conformal masking layer disposed on at least a portion of the dielectric layer. The electronic package further includes a routing layer disposed on at least a portion of the masking layer and a micro-via disposed at least in part in the conformal masking layer and the routing layer. Further, at least a portion of the routing layer forms a conformal electrically conductive layer in at least a portion of the micro-via. Also, the conformal masking layer is configured to define a size of the micro-via. The electronic package further includes a semiconductor die operatively coupled to the micro-via.

摘要翻译： 一种电子封装及其制造方法。 电子封装包括介电层和设置在电介质层的至少一部分上的保形掩模层。 电子封装还包括设置在掩模层的至少一部分上的布线层和至少部分地设置在保形掩模层和布线层中的微通孔。 此外，路由层的至少一部分在微通孔的至少一部分中形成共形导电层。 此外，共形掩模层被配置为限定微通孔的尺寸。 电子封装还包括可操作地耦合到微通孔的半导体管芯。

公开(公告)号：US20140242779A1

公开(公告)日：2014-08-28

申请号：US13954833

申请日：2013-07-30

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kenro NAKAMURA ,  Mitsuyoshi ENDO ,  Kazuyuki HIGASHI ,  Takashi SHIRONO

IPC分类号： H01L25/00 ,  H01L21/67

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/67092 ,  H01L21/6715 ,  H01L21/6836 ,  H01L23/3178 ,  H01L23/3185 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/08146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/75744 ,  H01L2224/80006 ,  H01L2224/80123 ,  H01L2224/80129 ,  H01L2224/83005 ,  H01L2224/83123 ,  H01L2224/83129 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2224/83 ,  H01L2224/80

摘要： According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.

摘要翻译： 根据一个实施例，半导体器件制造方法包括：将第一晶片和第二晶片彼此接合，以形成堆叠; 将附着有薄膜形状的填充材料的膜摩擦到位于第一晶片的斜面和第二晶片的斜面之间的间隙中，以填充与填充材料的间隙; 并使第一晶片变薄。

公开(公告)号：US09385104B2

公开(公告)日：2016-07-05

申请号：US14561572

申请日：2014-12-05

申请人： Shinkawa Ltd.

发明人： Daisuke Tani ,  Koichi Takahashi

IPC分类号： G05G15/00 ,  H01L23/00 ,  H01L23/544 ,  B32B37/00 ,  B32B41/00 ,  H01L23/48 ,  H01L25/00

CPC分类号： H01L24/75 ,  B32B37/0046 ,  B32B41/00 ,  B32B2309/72 ,  B32B2313/00 ,  B32B2457/14 ,  H01L23/481 ,  H01L23/544 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/13101 ,  H01L2224/16145 ,  H01L2224/32146 ,  H01L2224/75753 ,  H01L2224/75754 ,  H01L2224/75901 ,  H01L2224/8113 ,  H01L2224/81815 ,  H01L2224/81908 ,  H01L2224/83123 ,  H01L2224/83129 ,  H01L2224/8313 ,  H01L2924/014 ,  H01L2924/00014

摘要： Provided is a flip-chip bonding apparatus (500) capable of stacking and bonding a second-layer of the semiconductor chip (30) onto a first-layer of the semiconductor chip (20) having first through-silicon vias, the second-layer of the semiconductor chip (30) having second through-silicon vias at positions corresponding to the first through-silicon vias. The flip-chip bonding apparatus (500) includes: a double-view camera (16) configured to take images of thechips (20) and (30); and a control unit (50) having a relative-position detection program (53) for detecting relative positions of the first-layer of the semiconductor chip (20) and the second-layer of the semiconductor chip (30) that are stacked and bonded based on an image of the first through-silicon vias on a surface of the first-layer of the semiconductor chip (20) taken by the double-view camera (16) before stacked bonding, and an image of the second through-silicon vias on a surface of the second-layer of the semiconductor chip (30) taken by the double-view camera (16) after stacked bonding. This provides accurate connection between through-silicon vias using a simple method.

摘要翻译： 提供了一种倒装芯片接合装置（500），其能够将半导体芯片（30）的第二层叠层并接合到具有第一穿硅通孔的半导体芯片（20）的第一层上，第二层 的半导体芯片（30）在对应于第一穿通硅通孔的位置处具有第二穿硅通孔。 倒装芯片接合装置（500）包括：被配置为拍摄芯片（20）和（30）的图像的双视图相机（16）。 以及具有相对位置检测程序（53）的控制单元（50），用于检测半导体芯片（20）的第一层和半导体芯片（30）的第二层的层叠和结合的相对位置 基于在层叠结合之前由双视摄像机（16）取得的半导体芯片（20）的第一层的表面上的第一穿硅通孔的图像，以及第二穿硅通孔的图像 在层叠接合之后，由双视摄影机（16）拍摄的半导体芯片（30）的第二层的表面上。 这通过简单的方法提供了硅通孔之间的准确连接。

公开(公告)号：US09123717B2

公开(公告)日：2015-09-01

申请号：US13954833

申请日：2013-07-30

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kenro Nakamura ,  Mitsuyoshi Endo ,  Kazuyuki Higashi ,  Takashi Shirono

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L25/00 ,  H01L21/67 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/67092 ,  H01L21/6715 ,  H01L21/6836 ,  H01L23/3178 ,  H01L23/3185 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/08146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/75744 ,  H01L2224/80006 ,  H01L2224/80123 ,  H01L2224/80129 ,  H01L2224/83005 ,  H01L2224/83123 ,  H01L2224/83129 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2224/83 ,  H01L2224/80

摘要： According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.

摘要翻译： 根据一个实施例，半导体器件制造方法包括：将第一晶片和第二晶片彼此接合，以形成堆叠; 将附着有薄膜形状的填充材料的膜摩擦到位于第一晶片的斜面和第二晶片的斜面之间的间隙中，以填充与填充材料的间隙; 并使第一晶片变薄。

公开(公告)号：US20120315710A1

公开(公告)日：2012-12-13

申请号：US13578341

申请日：2011-02-01

申请人： Kazuyuki Hozawa ,  Kenichi Takeda ,  Mayu Aoki

发明人： Kazuyuki Hozawa ,  Kenichi Takeda ,  Mayu Aoki

IPC分类号： H01L21/82 ,  H01L21/66

CPC分类号： H01L22/20 ,  H01L21/6835 ,  H01L22/14 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11845 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/81193 ,  H01L2224/83002 ,  H01L2224/831 ,  H01L2224/83129 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/8389 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00

摘要： In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S401) in which a reconstituted wafer is prepared by replacing defective chips with non-defective chips, a step (S403) in which the reconstituted wafer and the base wafer are connected to one another by laminating, a step (S406) in which through-electrodes are formed in the reconstituted wafer, and a step (S409) in which a separate reconstituted wafer is laminated onto and connected to the reconstituted wafer having through-electrodes.

摘要翻译： 为了提供可以使用高生产率的W到W方法的半导体器件的制造方法，并且实现高产率，制造半导体器件的方法包括步骤（S401），其中通过替换有缺陷的芯片来制备重构的晶片 利用无缺陷的芯片，通过层叠将复原晶片和基底晶片彼此连接的步骤（S403），其中在重新构成的晶片中形成贯通电极的步骤（S406）和步骤（S409 ），其中将单独的重构晶片层压到具有通孔的重构晶片上并连接到其上。

公开(公告)号：US09437520B2

公开(公告)日：2016-09-06

申请号：US14774444

申请日：2013-03-13

申请人： Norimune Orimoto ,  Makoto Imai

发明人： Norimune Orimoto ,  Makoto Imai

IPC分类号： H01L23/36 ,  H01L23/367 ,  H01L23/00 ,  H01L23/13

CPC分类号： H01L23/3675 ,  H01L23/13 ,  H01L23/36 ,  H01L23/562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/26175 ,  H01L2224/29036 ,  H01L2224/291 ,  H01L2224/32014 ,  H01L2224/32113 ,  H01L2224/32245 ,  H01L2224/83129 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83815 ,  H01L2924/10161 ,  H01L2924/10272 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15159 ,  H01L2924/15165 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor element having a rectangular shape in a plan view, and a fixed member to which the semiconductor element is fixed. The semiconductor element is disposed so that a rectangular face of the semiconductor element is faced toward a surface of the fixed member. A part of the rectangular face of the semiconductor element is fixed to the surface of the fixed member. At least corner parts of the rectangular face of the semiconductor element are not fixed to the surface of the fixed member.

摘要翻译： 半导体器件包括在平面图中具有矩形形状的半导体元件和固定半导体元件的固定元件。 半导体元件设置成使得半导体元件的矩形面朝向固定构件的表面。 半导体元件的矩形面的一部分固定在固定部件的表面上。 半导体元件的矩形面的至少角部不固定到固定部件的表面。

公开(公告)号：US20160027714A1

公开(公告)日：2016-01-28

申请号：US14774444

申请日：2013-03-13

申请人： Norimune ORIMOTO ,  Makoto IMAI ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Norimune ORIMOTO ,  Makoto IMAI

IPC分类号： H01L23/367 ,  H01L23/00

CPC分类号： H01L23/3675 ,  H01L23/13 ,  H01L23/36 ,  H01L23/562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/26175 ,  H01L2224/29036 ,  H01L2224/291 ,  H01L2224/32014 ,  H01L2224/32113 ,  H01L2224/32245 ,  H01L2224/83129 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83815 ,  H01L2924/10161 ,  H01L2924/10272 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15159 ,  H01L2924/15165 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor element having a rectangular shape in a plan view, and a fixed member to which the semiconductor element is fixed. The semiconductor element is disposed so that a rectangular face of the semiconductor element is faced toward a surface of the fixed member. A part of the rectangular face of the semiconductor element is fixed to the surface of the fixed member. At least corner parts of the rectangular face of the semiconductor element are not fixed to the surface of the fixed member.

摘要翻译： 半导体器件包括在平面图中具有矩形形状的半导体元件和固定半导体元件的固定元件。 半导体元件设置成使得半导体元件的矩形面朝向固定构件的表面。 半导体元件的矩形面的一部分固定在固定部件的表面上。 半导体元件的矩形面的至少角部不固定到固定部件的表面。

公开(公告)号：US20150255411A1

公开(公告)日：2015-09-10

申请号：US14198509

申请日：2014-03-05

申请人： Omkar G. Karhade ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Amruthavalli P. Alur

发明人： Omkar G. Karhade ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Amruthavalli P. Alur

IPC分类号： H01L23/00 ,  G06F1/16 ,  H01L23/36

CPC分类号： H01L24/09 ,  G06F1/1658 ,  G06F1/1686 ,  G06F1/1688 ,  G06F1/1694 ,  G06F1/1698 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0807 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80138 ,  H01L2224/8085 ,  H01L2224/80897 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83127 ,  H01L2224/83129 ,  H01L2224/83855 ,  H01L2224/92242 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00012

摘要： Embodiments of the present disclosure are directed towards die-to-die bonding and associated integrated circuit (IC) package configurations. In one embodiment, a package assembly includes a package substrate having a solder resist layer disposed on a first side and a second side disposed opposite to the first side, a first die mounted on the first side and having an active side that is electrically coupled with the package substrate by one or more first die-level interconnects and a second die bonded with the active side of the first die using one or more second die-level interconnects, wherein at least a portion of the second die is disposed in a cavity that extends into the solder resist layer. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及芯片到芯片的结合和相关联的集成电路（IC）封装配置。 在一个实施例中，封装组件包括封装衬底，其具有设置在第一侧上的阻焊层和与第一侧相对设置的第二侧，安装在第一侧上的第一管芯，并且具有与 所述封装衬底通过一个或多个第一裸片级互连和使用一个或多个第二管芯级互连件与所述第一管芯的所述有源侧接合的第二管芯，其中所述第二管芯的至少一部分设置在腔中， 延伸到阻焊层中。 可以描述和/或要求保护其他实施例。