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公开(公告)号：WO2016007092A1
公开(公告)日：2016-01-14
申请号：PCT/SG2015/050206
申请日：2015-07-09
Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
Inventor： CHIDAMBARAM, Vivek , WICKRAMANAYAKA, Sunil , XU, Jinghui , DING, Zhipeng , SIOW, Li Yan
IPC: B23K35/00 , H01L23/495 , H01L23/488
CPC classification number: H01L21/50 , B23K35/00 , B23K35/002 , H01L23/488 , H01L25/0652 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
Abstract: A method for bonding wafers is provided. The method comprises the steps of providing a first wafer having an exposed first layer, the first layer comprising a first metal; and providing a second wafer having an exposed second layer, the second layer comprising a second metal, the first metal and the second metal capable of forming a eutectic mixture having a eutectic melting temperature. The method further comprises the steps of contacting the first layer with the second layer; and applying a predetermined pressure at a predetermined temperature to form a solid-state diffusion bond between the first layer and the second layer, wherein the predetermined temperature is below the eutectic melting temperature.
Abstract translation: 提供了一种接合晶片的方法。 该方法包括以下步骤：提供具有暴露的第一层的第一晶片，所述第一层包括第一金属; 以及提供具有暴露的第二层的第二晶片，所述第二层包括第二金属，所述第一金属和所述第二金属能够形成具有共晶熔融温度的共晶混合物。 该方法还包括使第一层与第二层接触的步骤; 以及在预定温度下施加预定压力以在所述第一层和所述第二层之间形成固态扩散接合，其中所述预定温度低于共晶熔融温度。
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公开(公告)号：WO2019147186A1
公开(公告)日：2019-08-01
申请号：PCT/SG2019/050039
申请日：2019-01-24
Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
Inventor： LI, Hongyu , XIE, Ling , CHONG, Ser Choong , WICKRAMANAYAKA, Sunil
IPC: H01L21/768 , H01L23/48
Abstract: Various embodiments may provide a method of forming an electrical connection structure. The method may include forming a cavity on a front surface of a substrate, the substrate including an electrically conductive pad, by etching through the electrically conductive pad. The method may also include forming one or more dielectric liner layers covering an inner surface of the cavity. The method may further include forming a via hole extending from the cavity by etching through the one or more dielectric liner layers, forming one or more further dielectric liner layers covering an inner surface of the via hole. The method may additionally include depositing a suitable electrically conductive material into the cavity and the via hole to form a conductive via having a first portion in the cavity and a second portion in the via hole, a diameter of the first portion different from a diameter of the second portion.
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公开(公告)号：WO2016114328A1
公开(公告)日：2016-07-21
申请号：PCT/JP2016/050892
申请日：2016-01-05
Inventor： KODAMA, Munehisa , OTSUKA, Yoshitaka , YAMAGUCHI, Kiyomitsu , YAMASAKI, Yutaka , WICKRAMANAYAKA, Sunil
IPC: H01L21/02 , B23K20/00 , H01L21/677
CPC classification number: H01L21/6831 , B23K20/023 , B23K20/24 , B23K20/26 , H01L21/67092 , H01L21/67103 , H01L21/67109 , H01L21/681
Abstract: A joint apparatus includes: a first holding unit which attracts and holds a first substrate; a second holding unit which attracts and holds a second substrate; an imaging unit which images, from outside a chamber, alignment marks provided on the first substrate and the second substrate via a through hole formed in the chamber and the first holding unit; a light source which radiates, from outside the chamber, light to the first substrate and the second substrate via a through hole formed in the chamber and the second holding unit; and a horizontal position adjustment unit which adjusts a horizontal position of the first holding unit.
Abstract translation: 接合装置包括：第一保持单元，其吸引并保持第一基板; 第二保持单元，其吸引并保持第二基板; 成像单元，其通过形成在所述室中的通孔和所述第一保持单元从室外图像设置在所述第一基板和所述第二基板上的对准标记; 通过形成在所述室和所述第二保持单元中的通孔，从所述室外部将光照射到所述第一基板和所述第二基板; 以及水平位置调整单元，其调节第一保持单元的水平位置。
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公开(公告)号：WO2016111374A1
公开(公告)日：2016-07-14
申请号：PCT/JP2016/050594
申请日：2016-01-05
Inventor： OZASA, Isao , WICKRAMANAYAKA, Sunil
CPC classification number: B23K20/021 , B23K2203/56
Abstract: A joint apparatus configured to join a plurality of chips arranged on a substrate to the substrate includes: a processing chamber that houses the substrate; a mounting table that is provided inside the processing chamber and mounts the substrate thereon; a heating mechanism that is provided in the mounting table and heats the substrate; and a gas supply mechanism that supplies a pressurizing gas to an inside of the processing chamber.
Abstract translation: 接合装置，被配置为将布置在基板上的多个芯片连接到所述基板上，包括：容纳所述基板的处理室; 安装台，其设置在处理室的内部并将基板安装在其上; 加热机构，其设置在所述安装台中并加热所述基板; 以及将加压气体供给到处理室的内部的气体供给机构。
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Patent Agency Ranking
公开(公告)号：WO2015195052A1
公开(公告)日：2015-12-23
申请号：PCT/SG2015/050173
申请日：2015-06-22
Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
Inventor： WICKRAMANAYAKA, Sunil , XIE, Ling , AW, Jerry Jie Li
CPC classification number: H01L24/81 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/0361 , H01L2224/03622 , H01L2224/0401 , H01L2224/05147 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11825 , H01L2224/1184 , H01L2224/11845 , H01L2224/119 , H01L2224/13023 , H01L2224/13026 , H01L2224/13147 , H01L2224/13562 , H01L2224/13611 , H01L2224/16225 , H01L2224/81022 , H01L2224/8109 , H01L2224/81097 , H01L2224/81099 , H01L2224/81192 , H01L2224/81193 , H01L2224/81203 , H01L2224/8181 , H01L2224/8182 , H01L2224/8183 , H01L2224/81986 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2924/3841 , H01L2924/00014 , H01L2224/11 , H01L2224/03 , H01L2924/014 , H01L2224/81 , H01L2224/9205
Abstract: A method for chip on wafer bonding is provided. The method includes the formation of a plurality of posts on at least one of a chip and a wafer, and a like plurality of contacts on the other of the chip and the wafer. After formation, a contact surface of each post is planarized, the respective planarized contact surface having a surface roughness height. A bonding material is then applied to at least one of the chip in a thickness no greater than the surface roughness height of the contact surface. The posts are then temporarily bonded to the contacts using the bonding material to stabilize a position of the chip relative to the wafer for permanent diffusion bonding of the chip to the wafer.
Abstract translation: 提供了一种晶片接合芯片的方法。 该方法包括在芯片和晶片中的至少一个上形成多个柱，以及在芯片和晶片的另一个上形成类似的多个触点。 在形成后，每个柱的接触表面被平坦化，相应的平坦化接触表面具有表面粗糙度高度。 然后将接合材料施加到不大于接触表面的表面粗糙度高度的厚度中的至少一个芯片。 然后使用接合材料将柱临时粘接到触点，以稳定芯片相对于晶片的位置，以将芯片永久扩散粘合到晶片。
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公开(公告)号：WO2015009238A1
公开(公告)日：2015-01-22
申请号：PCT/SG2014/000335
申请日：2014-07-16
Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
Inventor： WICKRAMANAYAKA, Sunil
CPC classification number: H01L24/83 , H01L21/563 , H01L24/743 , H01L24/75 , H01L24/81 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/50 , H01L2224/13009 , H01L2224/13147 , H01L2224/16145 , H01L2224/27515 , H01L2224/2919 , H01L2224/32145 , H01L2224/73104 , H01L2224/73204 , H01L2224/7501 , H01L2224/75102 , H01L2224/7511 , H01L2224/75184 , H01L2224/75264 , H01L2224/753 , H01L2224/7598 , H01L2224/81002 , H01L2224/81093 , H01L2224/81097 , H01L2224/81193 , H01L2224/81209 , H01L2224/81903 , H01L2224/81907 , H01L2224/83002 , H01L2224/8309 , H01L2224/83093 , H01L2224/83097 , H01L2224/8312 , H01L2224/83193 , H01L2224/83209 , H01L2224/83855 , H01L2224/83856 , H01L2224/83862 , H01L2224/83907 , H01L2224/83911 , H01L2224/9205 , H01L2224/9211 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2924/00014
Abstract: An apparatus and a method for chip-to-wafer integration is provided. The apparatus includes a coating module, a bonding module and a cleaning module. The method includes the steps of placing at least one chip on a wafer to form an integrated product, forming a film on the integrated product, such that the integrated product is substantially fluid-tight, and exerting a predetermined positive pressure on the film during permanent bonding of the at least one chip to the wafer. The method further includes the step of removing the film from the integrated product after permanent bonding of the at least one chip to the wafer.
Abstract translation: 提供了一种用于芯片到晶片集成的装置和方法。 该装置包括涂覆模块，粘合模块和清洁模块。 该方法包括以下步骤：将至少一个芯片放置在晶片上以形成集成的产品，在集成产品上形成膜，使得集成产品基本上是流体密封的，并且在永久性地在膜上施加预定的正压力 将至少一个芯片接合到晶片。 该方法还包括在将至少一个芯片永久地接合到晶片之后，从集成产品中去除膜的步骤。
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公开(公告)号：WO2017138885A1
公开(公告)日：2017-08-17
申请号：PCT/SG2017/050038
申请日：2017-01-26
Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
Inventor： CHIDAMBARAM, Vivek , SIOW, Li Yan , ZHANG, Qing Xin , WICKRAMANAYAKA, Sunil
CPC classification number: B81C1/00269
Abstract: There is provided a method of bonding a first substrate and a second substrate, the method comprising: providing an aluminium (Al) connection having a first width on one side of a first substrate; providing a germanium (Ge) connection having a second width on one side of a second substrate, wherein the second width is larger than the first width; and bonding the Al connection on the first substrate and the Ge connection on the second substrate by eutectic bonding of at least a portion of the Al connection and at least a portion of the Ge connection to form an Al-Ge eutectic melt, wherein the Al-Ge eutectic melt is confined within the second width of the Ge connection.
Abstract translation: 提供了一种结合第一基板和第二基板的方法，所述方法包括：在第一基板的一侧上提供具有第一宽度的铝（Al）连接; 在第二衬底的一侧上提供具有第二宽度的锗（Ge）连接，其中所述第二宽度大于所述第一宽度; 以及通过将所述Al连接的至少一部分与所述Ge连接的至少一部分共晶接合以形成Al-Ge共晶熔体，将所述第一衬底上的所述Al连接和所述第二衬底上的所述Ge连接结合，其中所述Al Ge共晶熔体被限制在Ge连接的第二宽度内。
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公开(公告)号：WO2016114329A1
公开(公告)日：2016-07-21
申请号：PCT/JP2016/050893
申请日：2016-01-05
Inventor： KODAMA, Munehisa , OTSUKA, Yoshitaka , YAMAGUCHI, Kiyomitsu , YAMASAKI, Yutaka , WICKRAMANAYAKA, Sunil
IPC: H01L21/02 , B23K20/00 , H01L21/683
CPC classification number: H01L21/6831 , B23K20/023 , B23K20/22 , B23K20/24 , B23K20/26 , H01L21/67092 , H01L21/67103 , H01L21/67109 , H01L21/681
Abstract: A joint apparatus includes: a first holding unit which attracts and holds a first substrate; a second holding unit which attracts and holds a second substrate; a pressurization unit which presses the first substrate and the second substrate against each other; a first adjustment unit which adjusts a position of the first holding unit along a first horizontal direction; and a second adjustment unit which adjusts the position of the first holding unit along a second horizontal direction perpendicular to the first horizontal direction. The first holding unit is rotated around a vertical axis using the first adjustment unit and the second adjustment unit.
Abstract translation: 接合装置包括：第一保持单元，其吸引并保持第一基板; 第二保持单元，其吸引并保持第二基板; 加压单元，其将所述第一基板和所述第二基板彼此挤压; 第一调整单元，其沿着第一水平方向调整所述第一保持单元的位置; 以及第二调整单元，其沿着与第一水平方向垂直的第二水平方向调节第一保持单元的位置。 第一保持单元使用第一调整单元和第二调整单元围绕垂直轴旋转。
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公开(公告)号：WO2016064350A1
公开(公告)日：2016-04-28
申请号：PCT/SG2015/050407
申请日：2015-10-23
Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
Inventor： XIE, Ling , WICKRAMANAYAKA, Sunil
IPC: H01L23/48 , H01L25/00 , H01L21/768 , H01L21/60
CPC classification number: H01L24/13 , H01L23/48 , H01L24/05 , H01L24/11 , H01L24/14 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05109 , H01L2224/05111 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/11464 , H01L2224/13109 , H01L2224/13111 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13565 , H01L2224/1357 , H01L2224/13609 , H01L2224/13611 , H01L2224/1369 , H01L2224/16145 , H01L2224/8112 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81825 , H01L2224/81856 , H01L2224/94 , H01L2225/06513 , H01L2924/14 , H01L2924/3841 , H01L2224/81
Abstract: A method for bonding a first substrate and a second substrate, the first substrate having at least one first connection extending from one side of the first substrate, the method comprising fabricating a first adhesive material around and along a height of the at least one first connection; and bonding the at least one first connection, the first adhesive material, and the second substrate.
Abstract translation: 一种用于接合第一基板和第二基板的方法，所述第一基板具有从所述第一基板的一侧延伸的至少一个第一连接，所述方法包括在所述至少一个第一连接的高度周围和沿着所述至少一个第一连接的高度 ; 以及接合所述至少一个第一连接部，所述第一粘合材料和所述第二基板。
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