公开(公告)号：EP2981158B1

公开(公告)日：2018-09-19

申请号：EP14774851.1

申请日：2014-03-26

Applicant: KYOCERA Corporation

Inventor： KAJITA, Satoshi ,  HAGIHARA, Mitsuhiro ,  MATSUMOTO, Yuuhei

IPC: H05K3/46 ,  H05K1/11 ,  H05K1/03 ,  H05K3/42

CPC classification number: H05K1/0306 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/09 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0038 ,  H05K3/421 ,  H05K3/4602 ,  H05K3/4655 ,  H05K2201/0116 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2201/2072

Abstract: A wiring board (3) in accordance with an embodiment of the invention includes: an inorganic insulating layer (13) having a via hole (V) formed so as to penetrate the inorganic insulating layer (13) in a thickness direction thereof; a conductive layer (11) disposed on the inorganic insulating layer (13); and a via conductor (12) which adheres to an inner wall (W) of the via hole (V) and is connected with the conductive layer (11). The inorganic insulating layer (13) includes a first section (33) including a plurality of inorganic insulating particles (16) partly connected to each other, and a resin portion (18) located in gaps (17) between the inorganic insulating particles (16), and a second section (34) which is interposed between the first section (33) and the via conductor (12), including a plurality of inorganic insulating particles (16) partly connected to each other, and a conducting portion (19) composed of part of the via conductor (12) which is located in gaps (17) between the inorganic insulating particles (16).

公开(公告)号：EP3200570A1

公开(公告)日：2017-08-02

申请号：EP17153635.2

申请日：2017-01-27

Applicant: At&S (China) Co., Ltd.

Inventor： Bauer-Öppinger, Nikolaus ,  Chen, ZhaoJian ,  Dou, Yucun ,  Tamm, Wilhelm

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0206 ,  H05K1/0209 ,  H05K1/09 ,  H05K1/112 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/0035 ,  H05K3/42 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2203/107 ,  H05K2203/1476

Abstract: The present invention relates to a component carrier (100) comprising a layer stack (101) formed of an electrically insulating structure and an electrically conductive structure. Furthermore, a bore (110) extends into the layer stack (101) and has a first bore section (111) with a first diameter (D1) and a connected second bore section (112) with a second diameter (D2) differing from the first diameter (D1). A thermally conductive material (102) fills substantially the entire bore (110). The bore is in particular formed by laser drilling.

Abstract translation: 本发明涉及包括由电绝缘结构和导电结构形成的叠层（101）的部件载体（100）。 此外，孔（110）延伸到层叠体（101）中并具有具有第一直径（D1）的第一孔部分（111）和具有不同于第二直径（D2）的第二直径（D2）的连接的第二孔部分 第一直径（D1）。 导热材料（102）基本填充整个孔（110）。 孔特别是通过激光钻孔形成。

公开(公告)号：EP3073523A4

公开(公告)日：2017-06-28

申请号：EP14864041

申请日：2014-11-19

Applicant: DAINIPPON PRINTING CO LTD

Inventor： KURAMOCHI SATORU ,  KOIWA SUMIO ,  YOSHIOKA HIDENORI

IPC: H01L23/32 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K1/11

CPC classification number: H01L23/49827 ,  H01L23/13 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/065 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/81805 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/381 ,  H05K1/115 ,  H05K3/28 ,  H05K3/445 ,  H05K2201/09154 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/0959 ,  H05K2201/09854 ,  H05K2203/0594 ,  H01L2924/00014 ,  H01L2924/05432 ,  H01L2924/0665 ,  H01L2924/07025

公开(公告)号：EP2981158A4

公开(公告)日：2017-01-18

申请号：EP14774851

申请日：2014-03-26

Applicant: KYOCERA CORP

Inventor： KAJITA SATOSHI ,  HAGIHARA MITSUHIRO ,  MATSUMOTO YUUHEI

IPC: H05K3/46 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K1/0306 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/09 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0038 ,  H05K3/421 ,  H05K3/4602 ,  H05K3/4655 ,  H05K2201/0116 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2201/2072

Abstract: A wiring board (3) in accordance with an embodiment of the invention includes: an inorganic insulating layer (13) having a via hole (V) formed so as to penetrate the inorganic insulating layer (13) in a thickness direction thereof; a conductive layer (11) disposed on the inorganic insulating layer (13); and a via conductor (12) which adheres to an inner wall (W) of the via hole (V) and is connected with the conductive layer (11). The inorganic insulating layer (13) includes a first section (33) including a plurality of inorganic insulating particles (16) partly connected to each other, and a resin portion (18) located in gaps (17) between the inorganic insulating particles (16), and a second section (34) which is interposed between the first section (33) and the via conductor (12), including a plurality of inorganic insulating particles (16) partly connected to each other, and a conducting portion (19) composed of part of the via conductor (12) which is located in gaps (17) between the inorganic insulating particles (16).

公开(公告)号：EP2829163A2

公开(公告)日：2015-01-28

申请号：EP13711574.7

申请日：2013-03-19

Applicant: Giesecke & Devrient GmbH

Inventor： BALDISCHWEILER, Michael ,  BOHN, Carsten

IPC: H05K1/11 ,  H05K3/40 ,  G06K19/077 ,  H05K1/09 ,  H05K1/16 ,  H05K3/12 ,  H05K3/00

CPC classification number: H05K1/116 ,  G06K19/0772 ,  G06K19/07754 ,  H05K1/092 ,  H05K1/165 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/1216 ,  H05K3/1233 ,  H05K3/4069 ,  H05K2201/0266 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09709 ,  H05K2201/0979 ,  H05K2201/09854 ,  H05K2201/10098 ,  H05K2203/1453

Abstract: A substrate (1) for a portable data carrier (10) comprises an electrical component (2, 3), such as an antenna, which has two parts applied on mutually opposite surfaces of the substrate (1). The parts of the electrical component (2, 3) comprise an electrically conductive material and are electrically conductively connected to one another in through-plating regions (4, 5, 6, 7) of the substrate (1) through perforations (8, 13) of the substrate (1). The perforations (8, 13) are produced by means of a laser and have a maximum width of a maximum of 20 μm. A through-plating region (4, 5, 6, 7) preferably has a multiplicity of perforations (8, 13) distributed over the through-plating region (4, 5, 6, 7).

Abstract translation: 用于便携式数据载体（10）的基板（1）包括诸如天线的电气部件（2,3），其具有施加在基板（1）的相互相对的表面上的两个部分。 电气部件（2,3）的部件包括导电材料，并且通过穿孔（8,13）在基板（1）的穿镀区域（4,5,6,7）中彼此导电地连接 ）的基板（1）。 穿孔（8,13）通过激光产生，最大宽度最大为20um。 穿透区域（4,5,6,7）优选地具有分布在通镀区域（4,5,6,7）上的多个穿孔（8,13）。

公开(公告)号：EP2763514A1

公开(公告)日：2014-08-06

申请号：EP14166887.1

申请日：2010-12-24

Applicant: Fujikura Ltd.

Inventor： Yamamoto, Satoshi ,  Suzuki, Takanao ,  Matsuyama, Masami

IPC: H05K1/11 ,  H01L23/12 ,  H05K3/40

CPC classification number: H05K3/0029 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2201/09836 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2203/025 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of manufacturing an interposer substrate that is provided with a planar substrate, and with a through hole interconnection that is formed by filling a through hole that connects together a first main surface and a second main surface of the substrate with a conductor. The through hole has a first aperture portion in the first main surface, and has a second aperture portion in the second main surface. The through hole is formed by irradiating the area of the substrate with laser light, so that when the through hole is viewed in a vertical cross-sectional view of the substrate, the through hole has a trapezoidal shape. The side faces of the trapezoid are not parallel to each other and are both inclined towards the same side.

Abstract translation: 一种制造具有平面基板的内插基板的制造方法，其特征在于，具有通过用导体填充将所述基板的第一主面与所述第二主面连接在一起的通孔而形成的贯通孔互连。 通孔在第一主表面具有第一开口部分，并且在第二主表面中具有第二开口部分。 通孔是通过用激光照射基板的区域而形成的，使得当在基板的垂直截面图中观察通孔时，通孔具有梯形形状。 梯形的侧面彼此不平行，并且朝向同一侧倾斜。

公开(公告)号：EP2101552B1

公开(公告)日：2014-05-07

申请号：EP08017982.3

申请日：2008-10-14

Applicant: Hitachi Ltd.

Inventor： Yamashita, Shiro ,  Yoshinari, Hideto

IPC: H05K3/30

CPC classification number: H05K1/119 ,  H05K1/0366 ,  H05K1/056 ,  H05K1/141 ,  H05K3/308 ,  H05K3/42 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2201/1059 ,  H05K2201/10803 ,  Y10S439/941

公开(公告)号：EP2575415A3

公开(公告)日：2013-11-27

申请号：EP12185974.8

申请日：2012-09-25

Applicant: Honeywell International Inc.

Inventor： Clark, Matthew ,  Galbrecht, Craig A. ,  Goblish, George L. ,  Koshiol, Myles

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H05K2201/068 ,  H05K2201/09027 ,  H05K2201/09063 ,  H05K2201/09854 ,  Y10T29/49124

Abstract: An apparatus includes a sheet of circuit board material, at least one electrically conductive trace positioned on the sheet of circuit board material, and at least one electrically conductive contact pad positioned on the sheet of circuit board material and coupled to the at least one electrically conductive trace. The apparatus further includes at least one deformation point configured to absorb stresses developed in the sheet of circuit board material when the sheet of circuit board material experiences resistance to expansion or compression caused by connection to an object resisting expansion or compression.

公开(公告)号：EP2165362B1

公开(公告)日：2012-02-08

申请号：EP08767260.6

申请日：2008-06-27

Applicant: ÅAC Microtec AB

Inventor： NILSSON, Peter

IPC: H01L23/48 ,  B81B7/00 ,  H01L21/768 ,  H01L23/52 ,  H05K3/40 ,  H05K3/42

CPC classification number: H05K3/4076 ,  B81B2207/07 ,  B81C1/00095 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H05K1/0306 ,  H05K3/002 ,  H05K3/0041 ,  H05K3/42 ,  H05K2201/09827 ,  H05K2201/09854 ,  H01L2924/00

Abstract: The present invention provides a wafer (3) comprising a through-wafer via (7) through the wafer (3) formed by a through-wafer via hole (9) and at least a first conductive coating (25). A substantially vertical sidewall (11) of the through-wafer via hole (9) except for a constriction (23) provides a reliable through-wafer via (7) occupying a small area on the wafer. The wafer (3) is preferably made of a semiconductor material, such as silicon, or a glass ceramic. A method for manufacturing such a wafer (3) is described.

公开(公告)号：EP1722613A4

公开(公告)日：2010-06-16

申请号：EP05710333

申请日：2005-02-17

Applicant: SANKYO KASEI KK

Inventor： YUMOTO TETSUO

IPC: H05K1/11 ,  H05K1/00 ,  H05K1/02 ,  H05K3/42

CPC classification number: G01R31/28 ,  H05K1/0284 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09236 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09854 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165 ,  Y10T29/49176