公开(公告)号：EP2015404A2

公开(公告)日：2009-01-14

申请号：EP08012609.7

申请日：2008-07-11

Applicant: YAMAHA CORPORATION

Inventor： Hattori, Atsuo

IPC: H01R13/11

CPC classification number: H05K3/365 ,  H01L2924/0002 ,  H01R12/52 ,  H01R12/718 ,  H01R13/11 ,  H01R13/20 ,  H05K3/326 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2201/209 ,  Y10T29/49204 ,  H01L2924/00

Abstract: An electronic component (1) includes a substrate (10), an interconnection element (102), and a connector (100). The interconnection element has conductivity. The interconnection element is present over the substrate. The connector is present on the interconnection element. The connector may further include, but is not limited to, a base (101), at least one stopper (17), and at least one sloped guiding surface. The base projects from the interconnection element in a first direction that is vertical to the surface of the substrate. At least one stopper projects from the base in a second direction that is parallel to the surface of the substrate. The one stopper has a stopper surface (103).

Abstract translation: 电子部件（1）包括基板（10），互连元件（102）和连接器（100）。 互连元件具有导电性。 互连元件存在于衬底上。 连接器存在于互连元件上。 连接器还可以包括但不限于底座（101），至少一个止动件（17）和至少一个倾斜的引导表面。 基底从互连元件沿垂直于基底表面的第一方向突出。 至少一个止动件在与基板的表面平行的第二方向上从基部突出。 一个止动件具有止动表面（103）。

公开(公告)号：EP1786034A3

公开(公告)日：2008-07-09

申请号：EP06023025.7

申请日：2006-11-06

Applicant: Semikron Elektronik GmbH & Co. KG Patentabteilung

Inventor： Göbl, Christian ,  Augustin, Karlheinz

IPC: H01L23/495 ,  H01L23/538 ,  H01L21/60 ,  H01L23/482

CPC classification number: H05K3/4007 ,  H01L23/49833 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L25/072 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/19107 ,  H01L2924/20757 ,  H05K1/0265 ,  H05K1/0393 ,  H05K1/09 ,  H05K3/4046 ,  H05K2201/0352 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2201/10166 ,  H05K2203/049 ,  H01L2924/00

Abstract: Es wird ein Leistungshalbleitermodul (10) mit einem Substrat (12), einer Verbundfolie (14) und mindestens einem Leistungshalbleiterbauelement (16) beschrieben, das zwischen dem Substrat (12) und der Verbundfolie (14) vorgesehen ist. Die Verbundfolie (14) weist eine dünne schaltstrukturierte Logikmetallschicht (26) und eine im Vergleich hierzu dicke schaltstrukturierte Leistungsmetallschicht (28) sowie zwischen diesen eine dünne elektrisch isolierende Kunststofffolie (24) auf. Die Verbundfolie (14) ist mit Kontaktnoppen (30) ausgebildet, die zur Kontaktierung mit dem mindestens einen Leistungshalbleiterbauelement (16) dienen. Zwischen der Logikmetallschicht (26) und der Leistungsmetallschicht (28) sind Durchkontaktierungen (32) vorgesehen. Die Kunststofffolie (24) ist im Bereich der jeweiligen Durchkontaktierung (32) an einem von der Logikmetallschicht (26) freien Bereich (36) mit einer Aussparung (34) ausgebildet. Ein Stück (38) eines flexiblen Dünndrahtes (40) erstreckt sich durch den freien Bereich (36) der Logikmetallschicht und durch die Aussparung (34) in der Kunststofffolie (24) hindurch und ist mit der Logikmetallschicht (26) und mit der Leistungsmetallschicht (28) durch Bondstellen (44, 48) kontaktiert.

公开(公告)号：EP1936677A2

公开(公告)日：2008-06-25

申请号：EP07024790.3

申请日：2007-12-20

Applicant: TDK Corporation

Inventor： Kawabata, Kenichi ,  Nagase, Kenji

IPC: H01L21/60 ,  H01L23/538

CPC classification number: H05K3/4007 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/185 ,  H05K3/061 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/09645 ,  H05K2201/10674 ,  H05K2203/054 ,  H05K2203/1152 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Provided is a wiring structure and the like which can completely connect a wiring layer to a body to be wired while keeping insulation between two adjacent wiring layers and realize high density packaging due to a narrowed pitch.
In a semiconductor-embedded substrate (1), a conductive pattern (13) is formed on both sides of a core substrate (11) and a semiconductor device (14) is placed in a resin layer (16) stacked over the core substrate. The resin layer has via-holes (19a,19b) so that the conductive pattern and a bump (14p) of the semiconductor device protrude from the resin layer. Inside the via-holes, the bump and conductive pattern are respectively connected to via-hole electrode portions (23a,23b) whose cross-sectional area has been increased toward the bottom of the via-hole. A void is defined between the via-hole electrode portion and upper portion of the inner wall of the via-hole.

Abstract translation: 本发明提供一种布线结构等，其可以将布线层完全连接到待布线的本体，同时保持两个相邻布线层之间的绝缘，并且由于间距变窄而实现高密度封装。 在半导体嵌入式基板（1）中，在芯基板（11）的两面形成导电图案（13），将半导体装置（14）配置在层叠在芯基板上的树脂层（16）中。 树脂层具有通孔（19a，19b），使得导电图案和半导体器件的凸块（14p）从树脂层突出。 在通孔内部，凸块和导电图案分别连接到横截面积已经朝向通孔底部增加的通孔电极部分（23a，23b）。 在通孔电极部分和通孔的内壁的上部之间限定空隙。

公开(公告)号：EP1632354B1

公开(公告)日：2007-12-12

申请号：EP05025554.6

申请日：2003-09-24

Applicant: Brother Kogyo Kabushiki Kaisha

Inventor： Shinkai, Yuji Technology Planning & IP Dept.

IPC: B41J2/14 ,  B41J2/16

CPC classification number: H05K3/363 ,  B41J2/14209 ,  B41J2/1609 ,  B41J2/1623 ,  B41J2002/14217 ,  B41J2002/14225 ,  B41J2002/14306 ,  B41J2002/14459 ,  B41J2002/14491 ,  B41J2202/20 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2201/09909 ,  H05K2201/10977 ,  H05K2201/2036 ,  Y10T29/42 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49179 ,  Y10T29/49401

公开(公告)号：EP1860691A1

公开(公告)日：2007-11-28

申请号：EP06715442.7

申请日：2006-03-09

Applicant: Hitachi Kyowa Engineering Co., Ltd.

Inventor： MATSUSHIMA, Naoki HITACHI, LTD. ,  TAKEMORI, Hideaki

IPC: H01L21/60 ,  H05K1/11 ,  H05K3/32 ,  H05K3/40

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05082 ,  H01L2224/05169 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48475 ,  H01L2224/48478 ,  H01L2224/4848 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/49175 ,  H01L2224/78301 ,  H01L2224/85009 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2224/85214 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/20752 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K3/328 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0154 ,  H05K2201/0367 ,  H05K2203/049 ,  Y10T29/49124 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00015

Abstract: To provide an electronic circuit board in which a conductive wire is excellently connected to a bonding pad formed directly on a polyimide film. The electronic circuit includes: a first layer metal pattern 3 formed on a substrate 1; a polyimide film 2 formed on the first layer metal pattern 3; and a second layer metal pattern formed on a surface of the polyimide film 2. A conductive bump 4 is formed on the surface of the second layer metal pattern 31 by ball-bonding to provide electrical connection with a semiconductor chip 7 bonded to the first layer metal pattern by die-bonding. The conductive bump 4 is electrically connected to an electrode 72 of the semiconductor chip 7 by wire bonding.

公开(公告)号：EP1818979A1

公开(公告)日：2007-08-15

申请号：EP05809664.5

申请日：2005-11-28

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： NISHIZAWA, Yoshihiko c/o Murata Manufact.Co.,Ltd. ,  IKEDA, Tetsuya c/o Murata Manufacturing Co., Ltd.

IPC: H01L23/02

CPC classification number: H05K1/0218 ,  B32B18/00 ,  C04B35/63 ,  C04B35/634 ,  C04B37/026 ,  C04B37/028 ,  C04B2235/656 ,  C04B2237/125 ,  C04B2237/32 ,  C04B2237/34 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/348 ,  C04B2237/40 ,  C04B2237/403 ,  C04B2237/405 ,  C04B2237/406 ,  C04B2237/408 ,  C04B2237/562 ,  C04B2237/62 ,  C04B2237/702 ,  C04B2237/704 ,  C04B2237/86 ,  C04B2237/88 ,  H01L21/4807 ,  H01L23/04 ,  H01L23/055 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K1/144 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/45015 ,  H01L2924/207

Abstract: As disclosed in Patent Document 1, when a shield case is reduced in thickness so as to promote reduction in height of an electronic component such as a hybrid IC, it is difficult to perform accurate processing of the shied case, for example, by bending because the shield case is made of metal. In addition, the shield case may be markedly deformed due to an external force applied to the shield case during picking up. With the configuration disclosed in Patent Document 2, since a ceramic cap is formed in a box-like shape, if the thickness of the ceramic cap is reduced for reduction in height of the electronic component, waviness may be generated at a top portion 2A, as shown in parts (a) and (b) of Fig. 18.
Accordingly, an electronic component 10 of the present invention includes a wiring board 11 having a wiring pattern 14, a surface mount device 12 mounted on an upper surface of the wiring board 11, and a cap 13 for covering the wiring board 11. The cap 13 includes a top portion 13A made of a flat ceramic member, and a leg portion 13B made of a columnar member having a height similar to a height of the surface mount devices 12.

Abstract translation: 如专利文献1所公开的那样，在为了促进混合集成电路等电子部件的高度化而使屏蔽壳体薄型化的情况下，难以通过例如弯曲来正确地处理屏蔽壳体， 屏蔽外壳由金属制成。 另外，由于在拾取期间施加到屏蔽壳的外力，屏蔽壳可能显着变形。 在专利文献2中公开的构造中，由于陶瓷帽形成为盒状，因此为了减小电子部件的高度而降低陶瓷帽的厚度，可能会在顶部2A产生波纹， 如图18的部分（a）和（b）所示。因此，本发明的电子部件10包括具有布线图案14的布线板11，安装在布线的上表面上的表面安装器件12 以及用于覆盖布线板11的盖13.盖13包括由扁平陶瓷构件制成的顶部13A和由具有与表面安装高度类似的高度的柱状构件制成的腿部13B 设备12。

公开(公告)号：EP1496537A3

公开(公告)日：2007-07-25

申请号：EP04254128.4

申请日：2004-07-09

Applicant: LG ELECTRONICS INC.

Inventor： Choi, Yong Gi ,  Kim, Soon Hak ,  Park, Seung Tea, No. 106-1402 Dongyang Hansin

IPC: H01J17/18 ,  H01J9/28 ,  H01R12/12

CPC classification number: H01J11/46 ,  H01J11/12 ,  H01L2224/73204 ,  H01R4/26 ,  H01R12/52 ,  H01R12/7076 ,  H01R13/22 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/0367

Abstract: There is disclosed a connection structure and method of a plasma display panel that is adaptive for preventing a short circuit caused by conductive ball mass and improving connection cohesiveness.
A connection structure of a plasma display panel according to an embodiment of the present invention includes a first substrate (53) having a plurality of panel-electrodes (54); a second substrate (51) having a plurality of connecting-electrodes (52) arranged to correspond to the panel-electrodes (54); and a connection member (55) located between the first substrate (53) and the second substrate (51) to directly connect the connecting-electrodes (52) with the panel-electrodes (54) upon compression.
Accordingly, there is no conductive ball, so the occurrence of short circuit caused by the conductive ball mass of prior art is prevented and, at the same time, the copper electrode (52) penetrates the panel-electrode (54), thereby improving connection cohesiveness.

公开(公告)号：EP1786250A1

公开(公告)日：2007-05-16

申请号：EP06255825.9

申请日：2006-11-14

Applicant: TDK Corporation

Inventor： Kobuke, Hisashi c/o TDK Corporation ,  Miyakoshi, Toshinobu c/o TDK Corporation ,  Uematsu, Hiroyuki c/o TDK Corporation

IPC: H05K3/46 ,  H05K3/40

CPC classification number: H05K3/281 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K1/0269 ,  H05K1/0306 ,  H05K3/4007 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/09881 ,  H05K2203/1189 ,  H05K2203/308 ,  H01L2924/00

Abstract: A composite wiring board includes a ceramic substrate (1), a resin layer (2, 3) in contact with at least one surface of the ceramic substrate and a sintered metal conductor (6) piercing through the resin layer. The composite wiring board is manufactured by a method including the steps of forming a through hole in a sheet (17) having a shrinkage-suppressing effect and filling the through hole with conductive paste (18) to obtain a sheet (15, 16, 61, 71, 81, 82) for formation of a conductor, firing the conductor formation sheet and a green sheet (11) for a substrate in their laminated state to obtain a ceramic substrate having a surface provided with a sintered metal conductor (6), removing from the surface of the ceramic substrate a fired product of the sheet having the shrinkage-suppressing effect and forming a resin layer (2, 3) on the surface of the ceramic substrate.

Abstract translation: 复合布线板包括陶瓷基板（1），与陶瓷基板的至少一个表面接触的树脂层（2,3）和穿过树脂层的烧结金属导体（6）。 复合布线板通过以下方法制造：在具有收缩抑制效果的片材（17）中形成通孔的步骤，并且用导电浆料（18）填充通孔以获得片材（15,16,61 ，71,81,82），用于形成导体，烧结导体形成片和用于基板的生片（11），以形成其层压状态，以获得具有设置有烧结金属导体（6）的表面的陶瓷基板， 从陶瓷基板的表面除去具有收缩抑制效果的片材的烧成品，并在陶瓷基板的表面上形成树脂层（2,3）。

公开(公告)号：EP1657059A3

公开(公告)日：2007-04-04

申请号：EP05024717.0

申请日：2005-11-11

Applicant: Brother Kogyo Kabushiki Kaisha

Inventor： Sugahara, Hiroto Technology Planning & IP Dept.

IPC: B41J2/14 ,  B41J2/16 ,  H01L41/09 ,  H05K3/36

CPC classification number: B41J2/1626 ,  B41J2/14233 ,  B41J2/161 ,  B41J2/1623 ,  B41J2/1634 ,  B41J2/1642 ,  B41J2/1646 ,  B41J2002/14266 ,  B41J2002/14491 ,  H01L41/0973 ,  H05K3/0058 ,  H05K3/363 ,  H05K2201/0367 ,  H05K2201/09036 ,  Y10T29/42

Abstract: A piezoelectric actuator (32) includes a supporting member (40) in which pressure chambers (44) are formed, a vibration plate (60) which is joined to a joining section (40a) of the supporting member, a piezoelectric layer (61) formed on the vibration plate, and an FPC (65) provided on the piezoelectric layer. A contact section (62a) of an electrode (62) formed on the piezoelectric layer and a terminal section (65a) of the FPC are electrically connected via a bump (66) formed on the terminal section. A recess (60a) is formed on an upper surface of the supporting member right below the bump. While joining the piezoelectric layer and a wire member, any damage of the piezoelectric layer and any poor connection do not occur.

公开(公告)号：EP1744605A2

公开(公告)日：2007-01-17

申请号：EP06014276.7

申请日：2006-07-10

Applicant: SEIKO EPSON CORPORATION

Inventor： Hashimoto, Nobuaki

IPC: H05K1/16

CPC classification number: H01L23/3114 ,  G02F1/13452 ,  H01L23/5228 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83856 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01066 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/167 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09909 ,  H05K2203/0361 ,  H01L2924/00 ,  H01L2924/01028

Abstract: An electronic board includes: a substrate (P); and a wiring pattern (20, 21) provided on the substrate (P) and having a part that forms a resistance element (R), the part having wiring specifications that are different from those of other parts.

Abstract translation: 电子板包括：基板（P）; 以及设置在所述基板（P）上并且具有形成电阻元件（R）的部分的布线图案（20,21），所述布线图案具有与其它部分不同的布线规格。