公开(公告)号：EP0782765B1

公开(公告)日：2000-06-28

申请号：EP95934106.6

申请日：1995-09-22

Applicant: SIEMENS N.V. ,  INTERUNIVERSITAIR MICRO-ELEKTRONICA CENTRUM VZW

Inventor： HEERMAN, Marcel ,  WILLE, Joost ,  VAN PUYMBROECK, Jozef ,  ROGGEN, Jean ,  BEYNE, Eric ,  VAN HOOF, Rita

IPC: H01L23/13 ,  H01L23/498

CPC classification number: H01L24/81 ,  B29L2031/3493 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/027 ,  H05K3/3431 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09045 ,  H05K2201/09118 ,  H01L2224/45099 ,  H01L2924/00

Abstract: The new structure comprises: an injection moulded three-dimensional substrate (S) made from an electrically insulating polymer; two-dimensionally configured polymer bumps (PS) formed during the injection-moulding process on the underside of the substrate (S); external connections (AA) formed on the polymer bumps (PS) by solderable end surfaces; conducting paths (LZ) at least on the underside of the substrate (S) to connect the external connections (AA) to inner connections (IA1); and at least one chip (C1) mounted on the substrate (S) with connections (CA1) which are electro-conductively linked to the inner connections. The novel structure, which is suitable for single-, few- or multi-chip modules, combines the advantages of a Ball Grid Array with those of MID (Moulded Interconnection Devices) technology, and the manufacture and metallization of the polymer bumps (PS) can be done within the framework of the process steps needed for MID technology and at minimal additional cost.

Abstract translation: 聚合物螺柱网格阵列具有电绝缘聚合物的三维基底（S），平坦表面设有聚合物柱（PS），每个具有外部末端（AA）。 电导体路径将外部端子耦合到连接到安装在基板上的半导体芯片（C1）的端子的内部端子（IA1）。 县。 聚合物螺柱的模制和金属化是使用模制互连装置技术实现的，而不需要额外的步骤。

公开(公告)号：EP0806127A4

公开(公告)日：1999-04-21

申请号：EP95943682

申请日：1995-12-07

Applicant: RES ORGANIZATION FOR CIRCUIT K

Inventor： ROBERTS JOSEPH A

IPC: B21D22/02 ,  B21D31/00 ,  H01R31/00 ,  H05K1/03 ,  H05K3/04 ,  H05K3/28 ,  H05K3/32 ,  H05K3/38 ,  H05K3/46 ,  H05K7/14 ,  H05K9/00 ,  H05K1/00

CPC classification number: H01R31/00 ,  H05K1/036 ,  H05K3/045 ,  H05K3/281 ,  H05K3/328 ,  H05K3/386 ,  H05K3/4614 ,  H05K3/4647 ,  H05K7/1451 ,  H05K9/0039 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0382 ,  H05K2201/0715 ,  H05K2203/025 ,  H05K2203/063 ,  Y10T29/49155

Abstract: A process and apparatus for producing supported conductive networks (1) which can be flexible or rigid, having densely packed circuits (3). The process and apparatus for making the conductive network (1) involves forming a conductive material (8) supported on a 'dynamic pressure cushion' into a non-planar pattern defining the desired conductive circuits (3) in relation to a fixed reference plane (32). The 'dynamic pressure cushion' is a material having suitable viscosity and flow characteristics to flow out from under the conductive material (8) as it is being formed and fill up any voids. To ensure that the 'dynamic pressure cushion' properly flows without deforming the desired circuits (3), the die (6) used to form the conductive material (8) is provided with a material flow control grid and material expansion troughs. After forming the unwanted material is then mechanically removed in dimensional relation to the reference plane (32) leaving the desired conductive circuits (3).

公开(公告)号：EP0863426A1

公开(公告)日：1998-09-09

申请号：EP98103837.5

申请日：1998-03-04

Applicant: Sharp Kabushiki Kaisha

Inventor： Shiota, Motoji ,  Inada, Kiyoshi ,  Yoshida, Hirokazu

IPC: G02F1/13 ,  H01L21/60

CPC classification number: H01L24/83 ,  G02F1/13452 ,  H01L24/12 ,  H01L24/16 ,  H01L24/28 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/323 ,  H05K2201/0367 ,  H05K2201/09709 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A liquid crystal display device according to the present invention includes a substrate (3a) provided with a line pattern, and a circuit element (1) electrically connected to the line pattern via a conductive layer (2). The line pattern has at least one bonding pad (6). The circuit element has at least one electrode pad (4). The at least one electrode pad has a plurality of bump electrodes (5a,5b) provided thereon. The at least one electrode pad (4) is electrically connected to the at least one bonding pad (6) via the conductive layer (2) which is provided between the plurality of bump electrodes and the bonding pad facing the plurality of bump electrodes, where the conductive layer is an insulative material (1) having conductive particles (7) dispersed throughout.

Abstract translation: 根据本发明的液晶显示装置包括设置有线图案的基板（3a）和经由导电层（2）电连接到线图案的电路元件（1）。 线路图案具有至少一个键合焊盘（6）。 电路元件具有至少一个电极垫（4）。 该至少一个电极焊盘具有设置在其上的多个凸块电极（5a，5b）。 所述至少一个电极焊盘（4）经由设置在所述多个凸块电极和面对所述多个凸块电极的焊盘之间的导电层（2）电连接到所述至少一个焊盘（6），其中， 导电层是具有分散于其中的导电颗粒（7）的绝缘材料（1）。

公开(公告)号：EP0861018A2

公开(公告)日：1998-08-26

申请号：EP98103046.3

申请日：1998-02-20

Applicant: RICOH MICROELECTRONICS CO., LTD.

Inventor： Kinoshita, Makoto

IPC: H05K3/34 ,  H05K3/12 ,  B41M1/10

CPC classification number: H01L24/81 ,  B41M1/10 ,  H01L21/4853 ,  H01L21/4867 ,  H01L24/75 ,  H01L2224/10165 ,  H01L2224/742 ,  H01L2224/75 ,  H01L2224/8014 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K3/207 ,  H05K3/3468 ,  H05K2201/0367 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/074 ,  H05K2203/085 ,  H05K2203/086 ,  Y10S428/901 ,  Y10T29/49124 ,  Y10T29/49155 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/81805

Abstract: An intaglio printing method and an intaglio printer are proposed, which are suitable for forming a wiring pattern and/or bumps such as bump electrodes on a print receiving material on which printing is to be performed, such as a substrate and a semiconductor package, using a paste or a fused metal. In addition, a method of forming the wiring pattern and the bumps such as bump electrodes on the printing substrate, using the intaglio printing method, a method for forming a wiring pattern, an apparatus for carrying out the method of forming the wiring pattern, the bump electrode and the wiring pattern are proposed.

Abstract translation: 凹版印刷法和凹版印刷打印机是提出一种适合用于形成布线图案和/或凸块：诸如在打印在其上的打印接受材料凸块电极将被执行，检查作为基板和半导体封装，采用 糊或熔融金属。 另外，在形成上述布线图形和所述凸块的方法：如在印刷基板凸块电极，采用凹版印刷法，用于形成布线图案的方法，以装置用于进行形成布线图案的方法，该 凸块电极和配线图案的提议。

公开(公告)号：EP0853342A1

公开(公告)日：1998-07-15

申请号：EP97930854.1

申请日：1997-07-22

Applicant: HONDA GIKEN KOGYO KABUSHIKI KAISHA

Inventor： INOUE, Masajiro

IPC: H01L25/04 ,  H01L21/60 ,  H01L23/32

CPC classification number: H01R13/2414 ,  H01L21/563 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/0106 ,  H01L2924/01063 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/15312 ,  H01L2924/1579 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/0064 ,  H05K3/28 ,  H05K3/321 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/09909 ,  H05K2201/10303 ,  H05K2201/10424 ,  H05K2201/10674 ,  H05K2201/10704 ,  Y10T29/4913 ,  Y10T29/49147 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/05442 ,  H01L2224/05599

Abstract: A plug-in type electronic control unit is comprised of a wiring board, a plurality of electronic parts mounted on one surface of the wiring board by utilizing a wireless bonding process, and a plug member mounted on the other surface of the wiring board by utilizing a wireless bonding process. It is possible to suppress the planar extent of the unit by such a laminated structure, and to suppress the extent of the unit in a laminating direction by the employment of the wireless bonding process. Thus, it is possible to achieve a reduction in size of the plug-in type electronic control unit.

Abstract translation: 插电式电子控制单元由布线板，通过利用无线接合工艺安装在布线板的一个表面上的多个电子部件和通过利用布线板安装在布线板的另一个表面上的插头构件 无线绑定过程。 通过这样的层叠结构，可以抑制单位的平面化程度，并且通过使用无线接合处理来抑制单元在层叠方向上的程度。 因此，可以实现插入式电子控制单元的尺寸的减小。

公开(公告)号：EP0849983A1

公开(公告)日：1998-06-24

申请号：EP96402845.0

申请日：1996-12-20

Applicant: ALCATEL ALSTHOM COMPAGNIE GENERALE D'ELECTRICITE ,  IMEC

Inventor： Peeters, Joris Antonia Franciscus ,  Vandam, Louis Joseph ,  Allaert, Koenraad Juliaan Georges ,  Ackaert, Ann Marie ,  van Calster, André ,  Vereeken, Maria Eugenie André ,  Zhang, Suixin ,  de Baets, Joahn ,  Vandervelde, Bart Leo Alfons Maurice

IPC: H05K3/40 ,  H05K3/24 ,  H01L21/48 ,  H01L23/492

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K1/114 ,  H05K3/0094 ,  H05K3/062 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/0361 ,  H05K2203/072 ,  H01L2924/00

Abstract: A process to create metallic stand-offs or studs on a printed circuit board (PCB). The process allows to obtain studs constituted by three successive layers of metal (Cu1, Cu2 and Cu3 or Ni) of which at least the two first layers are made of copper. The height of the so-create stand-off is sufficient to use it in the flip chip technology to assemble chips to a printed circuit board. The present process is implemented according either to the electro-plating (galvano-plating) or to the electrochemical-plating technique.

Abstract translation: 在印刷电路板（PCB）上创建金属支座或螺柱的过程。 该方法允许获得由三个连续的金属层（Cu1，Cu2和Cu3或Ni）构成的柱，其中至少两个第一层由铜制成。 所以这样创建的支架的高度足以在倒装芯片技术中使用它将芯片组装到印刷电路板上。 本方法根据电镀（电镀）或电化学镀技术来实现。

公开(公告)号：EP0844657A1

公开(公告)日：1998-05-27

申请号：EP97925302.8

申请日：1997-06-06

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： TSUKAHARA, Norihito, 3-403, Esutatakanohara

IPC: H01L21/60

CPC classification number: H01L24/29 ,  H01L21/563 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/743 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/3511 ,  H05K1/0393 ,  H05K1/113 ,  H05K3/321 ,  H05K3/4069 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/1189 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T156/1054 ,  Y10T156/1062 ,  Y10T156/107 ,  Y10T156/109 ,  Y10T156/1092 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: This is to present a mounting method of semiconductor element capable of joining an electrode of a semiconductor element and a circuit of a circuit board at high reliability.
It comprises a step of forming an external electrode terminal 33 by filling a hole 8 formed in a circuit board 4 with a conductive paste 7, a step of positioning the external electrode terminal 33 and a protruding bump 3 formed on an electrode 2 of a semiconductor 1, and a step of pressing the semiconductor element 1 to contact between the conductive paste 7 in the hole 8 and the protruding bump 3, thereby electrically connecting the electrode 2 of the semiconductor element 1 and the external electrode terminal 33 of the circuit board 4.

Abstract translation: 这是为了提供能够高可靠性地接合半导体元件的电极和电路板的电路的半导体元件的安装方法。 它包括通过用导电浆料7填充形成在电路板4中的孔8形成外部电极端子33的步骤，定位外部电极端子33的步骤和形成在半导体的电极2上的突起3 如图1所示，并且按压半导体元件1以接触孔8中的导电膏7和突出凸起3之间的步骤，从而将半导体元件1的电极2和电路板4的外部电极端子33电连接 。

公开(公告)号：EP0843357A1

公开(公告)日：1998-05-20

申请号：EP97309161.4

申请日：1997-11-13

Applicant: TEXAS INSTRUMENTS INC.

Inventor： Abbott, Donald C.

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0554 ,  H05K2203/1394 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A method for manufacturing a column grid array semiconductor package (10,210) may include the steps of providing a substrate material (14,114,214) having a first side (16,116) and a second side (18), forming a plurality of holes (36,136,236) in the substrate (14,114,214), forming contacts (24,124) on the first surface (16,116) of the substrate (14,114,214), filling the plurality of holes (36,136,236) with a conductive material (32,132,232) to an extent that an extension portion (28,128,228) is formed on the second side (18) of the substrate (14,114,214) to which an electrical contact may be made. The extension portion (28,128,228) may be coated with a capping material (40,140,240). The holes (36,136,236) may be filled with the conductive material (32,132,232) by forming a resist layer (146,246) over the hole (36,136,236) on the first side (16,116) of the substrate (14,114,214) and filling the holes (36,136,236) with the conductive material (32,132,232). The resist (146,246) may then be removed.

Abstract translation: 一种用于制造列栅阵列半导体封装（10,210）的方法可以包括以下步骤：提供具有第一侧（16,116）和第二侧（18）的衬底材料（14,114,214），形成多个孔（36,136,236） 衬底（14,114,214），在衬底（14,114,214）的第一表面（16,116）上形成接触（24,124），用导电材料（32,132,232）将导电材料（32,132,232）填充到多个孔（36,136,236）中，延伸部分（28,128,228） 形成在可以形成电接触的基板（14,114,214）的第二侧（18）上。 延伸部分（28,128,228）可涂覆有封盖材料（40,140,​​240）。 通过在衬底（14,114,214）的第一侧（16,116）上的孔（36,136,236）上方形成抗蚀剂层（146,246），并且用孔（36,136,236）填充孔（36,136,236），孔可以填充导电材料（32,132,232） 导电材料（32,132,232）。 然后可以除去抗蚀剂（146,246）。

公开(公告)号：EP0834917A1

公开(公告)日：1998-04-08

申请号：EP96115745.0

申请日：1996-10-01

Applicant: NITTO DENKO CORPORATION

Inventor： Naito, Toshiki, Nitto Denko Corp. ,  Ouchi, Kazuo, Nitto Denko Corp.

IPC: H01L23/31 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L23/4985 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/1572 ,  H01L2924/00

Abstract: Disclosed are a film carrier comprising an insulating layer (2') having laid therein an electrically conductive circuit such that the circuit is not exposed on the surface thereof, wherein conductive passages from the conductive circuit to one surface of the insulating layer (2') are formed in the insulating layer and via holes (3') from said conductive circuit to the other surface of the insulating layer (2') are formed and a semiconductor device prepared by mounting a semiconductor element (5) on the insulating layer (2') of the film carrier. The film carrier can sufficiently correspond to pitch-fining and high-density mounting of a semiconductor element wiring, can surely perform the connecting operation of inner lead bonding and outer lead bonding, and gives the mounting area of as small as possible.

Abstract translation: 公开了一种薄膜载体，其包括绝缘层（2'），其中放置有导电电路，使得该电路不在其表面上露出，其中从导电电路到绝缘层（2'）的一个表面的导电通路 形成在所述绝缘层中，并且形成从所述导电电路到绝缘层（2'）的另一个表面的通孔（3'）和通过将半导体元件（5）安装在绝缘层（2'）上而制备的半导体器件 '）的电影载体。 薄膜载体可以充分地对应于半导体元件布线的间距精细和高密度安装，可以可靠地执行内部引线接合和外部引线接合的连接操作，并且使安装面积尽可能小。

公开(公告)号：EP0782765A1

公开(公告)日：1997-07-09

申请号：EP95934106.0

申请日：1995-09-22

Applicant: SIEMENS N.V. ,  INTERUNIVERSITAIR MICRO-ELEKTRONICA CENTRUM VZW

Inventor： HEERMAN, Marcel ,  WILLE, Joost ,  VAN PUYMBROECK, Jozef ,  ROGGEN, Jean ,  BEYNE, Eric ,  VAN HOOF, Rita

IPC: H01L23 ,  H01L21 ,  H05K3

CPC classification number: H01L24/81 ,  B29L2031/3493 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/027 ,  H05K3/3431 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09045 ,  H05K2201/09118 ,  H01L2224/45099 ,  H01L2924/00

Abstract: The new structure comprises: an injection moulded three-dimensional substrate (S) made from an electrically insulating polymer; two-dimensionally configured polymer bumps (PS) formed during the injection-moulding process on the underside of the substrate (S); external connections (AA) formed on the polymer bumps (PS) by solderable end surfaces; conducting paths (LZ) at least on the underside of the substrate (S) to connect the external connections (AA) to inner connections (IA1); and at least one chip (C1) mounted on the substrate (S) with connections (CA1) which are electro-conductively linked to the inner connections. The novel structure, which is suitable for single-, few- or multi-chip modules, combines the advantages of a Ball Grid Array with those of MID (Moulded Interconnection Devices) technology, and the manufacture and metallization of the polymer bumps (PS) can be done within the framework of the process steps needed for MID technology and at minimal additional cost.

Abstract translation: 聚合物螺柱网格阵列具有电绝缘聚合物的三维基底（S），平坦表面设有聚合物柱（PS），每个具有外部末端（AA）。 电导体路径将外部端子耦合到连接到安装在基板上的半导体芯片（C1）的端子的内部端子（IA1）。 县。 聚合物螺柱的模制和金属化是使用模制互连装置技术实现的，而不需要额外的步骤。