公开(公告)号：EP0989789A3

公开(公告)日：2001-06-13

申请号：EP99307407.9

申请日：1999-09-17

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA

Inventor： Nojioka, Shinichi

IPC: H05K1/11 ,  H05K3/34

CPC classification number: H05K3/3452 ,  H05K1/116 ,  H05K3/3447 ,  H05K2201/09381 ,  H05K2201/099 ,  H05K2201/10651 ,  Y10S428/901 ,  Y10T428/24281 ,  Y10T428/24802

Abstract: A printed wiring board with an increased strength of solder is provided by preventing solder bridge formation and increasing the amount of solder adherent thereto. A land (1) serving as a soldering foundation is formed in a star-shape, to minimize the proximal peripheral length (L2) between adjacent lands spaced distance (L1) apart, thus reducing the possibility of solder bridge formation. Since the star-shaped land (1) has a greater area than a rhombic land of identical size, the amount of solder adherent thereto is greater than that of the rhombic land, thus enabling to increase the strength of solder.

Abstract translation: 通过防止焊料桥形成和增加附着于其上的焊料的量来提供具有增加的焊料强度的印刷线路板。 用作焊接基座的焊盘（1）形成为星形，以使间隔距离（L1）的相邻焊盘之间的近端周长（L2）最小化，从而减少形成焊料桥的可能性。 由于星形土地（1）的面积大于相同尺寸的菱形土地，因此附着于其上的焊料的量大于菱形，因此能够提高焊料的强度。

公开(公告)号：EP0996322A2

公开(公告)日：2000-04-26

申请号：EP99308015.9

申请日：1999-10-12

Applicant: ALPS ELECTRIC CO., LTD.

Inventor： Harada, Hiroshi ,  Terashima, Kiminori

IPC: H05K3/34 ,  H05K3/36

CPC classification number: H05K3/3452 ,  H05K1/141 ,  H05K3/3442 ,  H05K2201/09181 ,  H05K2201/09381 ,  H05K2201/099 ,  H05K2201/10984 ,  H05K2203/042 ,  Y02P70/613

Abstract: The electronic circuit unit of the present invention is provided with the broad width lands (4a) and the thin width lands (4b) tied with the broad width lands, which are configured by a solder resist (5) that is formed on the surface of the circuit board (1). Owing to this configuration, the solders placed on the thin width lands (4b) are drawn toward the broad width lands (4a), which increases the quantity of the solder build-up on the broad width lands, and accompanied with this increase, swells the heights of the solder build-up on the broad width lands. Thus, the electronic circuit unit of the present invention ensures the soldering.

Abstract translation: 本发明的电子电路部设置有宽幅的土地（4a）和所述薄宽度土地（4b）上的宽幅的土地，其通过焊料配置并列抗蚀剂（5）没有被形成的表面上 所述电路板（1）。 由于该构造，放置在薄宽度土地（4b）的焊料被拉向广阔的宽度的土地（4a）中，这增加了在宽的宽度的土地焊料积聚的量，并与这种增加的陪同下，膨胀 上广阔的宽度土地上的焊料堆积的高度。 因此，本发明的电子电路单元确保焊接。

公开(公告)号：EP0814643A2

公开(公告)日：1997-12-29

申请号：EP97109609

申请日：1997-06-12

Applicant: IBIDEN CO LTD

Inventor： ASAI MOTOO ,  KAWAMURA YOICHIRO

IPC: H05K3/46 ,  H01L23/12 ,  H01L23/498 ,  H01L23/538 ,  H05K1/11 ,  H05K3/06 ,  H05K3/34

CPC classification number: H05K1/112 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/3478 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  H05K2201/10734 ,  H05K2203/0156 ,  H05K2203/0338 ,  H05K2203/0405 ,  H05K2203/043 ,  H01L2924/00

Abstract: A multilayer printed circuit board comprises a core substrate, multilayer wiring layers formed on the substrate by alternately laminating an interlaminar insulating layer and conductor circuit, and a group of solder pads having solder bumps planarly arranged on an outermost surface of the multilayer wiring layers, in which the solder pads located from first row to fifth row from an outer position of the solder pad group are constructed with flat pads connected to conductor pattern located on the outermost surface and solder bumps formed on the surfaces of the pads, while the solder pad group other than these solder pads are constructed with viaholes connected to flat innerlayer pad group located in an inner layer and solder bumps formed in recess portions of the viaholes, and the solder pads located from first row to fifth row from an outer position of the innerlayer pad group are constructed with flat pads connected to conductor patterns in the same layer as the innerlayer pad group, while the innerlayer pad groups other than the pads are constituted with flat pads connected to a further innerlayer flat pad group located inward the above innerlayer through viaholes.

Abstract translation: 多层印刷电路板包括芯基板，通过交替层叠层间绝缘层和导体电路而形成在基板上的多层布线层，以及一组焊料凸块，其平坦地布置在多层布线层的最外表面上， 其中焊盘从焊料焊盘组的外部位置位于第一行至第五行的焊盘被构造为连接到位于最外表面上的导体图案的平坦焊盘和形成在焊盘表面上的焊料凸块，而焊盘组 除了这些焊盘之外，构成了连接到位于内层中的平坦内层焊盘组的通孔和形成在通孔的凹部中的焊料凸块以及从内层焊盘的外部位置位于第一行至第五行的焊盘 在与内层垫组相同的层中的导体图案上连接有平垫， 而除了焊盘之外的内层焊盘组由通过通孔连接到位于上层内层的另一内层平垫组的平垫组成。

公开(公告)号：EP0361752A2

公开(公告)日：1990-04-04

申请号：EP89309479.7

申请日：1989-09-19

Applicant: AT&T Corp.

Inventor： Durnwirth, Roy Karl, Jr. ,  George, John Emanuel ,  Morton, Kim Leslie

IPC: H05K3/34 ,  H05K3/24

CPC classification number: H05K3/3473 ,  H05K3/062 ,  H05K3/108 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2203/0361 ,  H05K2203/043

Abstract: Disclosed is a method of providing solder (22) on selected portions of a printed circuit board (10). Solder (14) is first electroplated over copper conductor patterns (16, 11, 13) on the board by means of a first photoresist layer (12). After stripping the first photoresist, a second photoresist layer (15) is laminated over the board and developed to expose selected portions of the solder. The exposed portions are selectively stripped. The copper exposed by the selective stripping is then subjected to a scrubbing while the photoresist protects the remaining solder, and the second photoresist is removed.

Abstract translation: 公开了一种在印刷电路板（10）的选定部分上提供焊料（22）的方法。 首先通过第一光致抗蚀剂层（12）将焊料（14）电镀在板上的铜导体图案（16,11,13）上。 在剥离第一光致抗蚀剂之后，将第二光致抗蚀剂层（15）层叠在板上并显影以暴露焊料的选定部分。 暴露部分被选择性剥离。 然后通过选择性剥离曝光的铜进行洗涤，同时光致抗蚀剂保护剩余的焊料，并除去第二光致抗蚀剂。

公开(公告)号：EP2134147B1

公开(公告)日：2018-08-08

申请号：EP09161821.5

申请日：2009-06-03

Applicant: Valeo Equipements Electriques Moteur

Inventor： Mandion, Thierry ,  Chemin, Michaël

IPC: H05K1/02 ,  H05K3/34 ,  H05K1/11 ,  H05K3/30

CPC classification number: H05K3/3421 ,  H01L2924/0002 ,  H05K1/0269 ,  H05K1/111 ,  H05K3/303 ,  H05K3/3452 ,  H05K2201/0979 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/09918 ,  H05K2201/10166 ,  H05K2203/166 ,  Y02P70/613 ,  H01L2924/00

公开(公告)号：EP3233345A1

公开(公告)日：2017-10-25

申请号：EP15808076.2

申请日：2015-11-18

Applicant: ZKW Group GmbH

Inventor： EDLINGER, Erik

IPC: B23K1/00 ,  H05K3/34 ,  H05K1/11 ,  H05K3/30

CPC classification number: B23K1/0016 ,  B23K1/008 ,  B23K1/203 ,  B23K2201/42 ,  H05K1/111 ,  H05K3/305 ,  H05K3/3431 ,  H05K3/3452 ,  H05K3/3484 ,  H05K3/3494 ,  H05K2201/099 ,  H05K2203/042 ,  H05K2203/1178

Abstract: The invention relates to a method for the soldering connection at least of one electronic component (104, 204, 304, 404, 504) to a carrier plate (100, 200, 300, 400, 500), wherein the carrier plate has at least one carrier plate contact surface (102, 202, 302, 402, 502) and the at least one electronic component has at least one corresponding component contact surface (105), wherein the at least one carrier plate contact surface is surrounded by a solder resist layer (101, 201, 301, 401, 401) that abuts the at least one carrier plate contact surface, wherein the method comprises the following steps: a) applying, at least in sections, solder paste (106, 206, 306, 406, 506) to the solder resist layer (101, 201, 301, 401, 501) and with minimal overlapping with the carrier plate contact surface (102, 202, 302, 402, 502) abutting the solder resist layer; b) providing the carrier plate with the at least one electronic component (104, 204, 304, 404, 504), wherein the at least one component contact surface (105) at least partially covers the corresponding at least one carrier plate contact surface (102, 202, 302, 402, 502); and c) heating the solder paste (106, 206, 306, 406, 506) to produce a soldered connection between the carrier plate and the at least one component.

Abstract translation: 本发明涉及一种用于将至少一个电子部件（104,204,304,404,504）焊接到承载板（100,200,300,400,500）的方法，其中承载板至少具有 一个承载板接触表面（102,202,302,402,502），并且所述至少一个电子部件具有至少一个对应的部件接触表面（105），其中所述至少一个承载板接触表面被阻焊层 （101,201,301,401,401），其邻接所述至少一个承载板接触表面，其中所述方法包括以下步骤：a）至少部分地施加焊膏（106,206,306,406） ，506）与所述阻焊层（101,201,301,401,501）并且与邻接所述阻焊层的所述载体板接触表面（102,202,302,402,502）的重叠最小; b）为所述承载板提供所述至少一个电子部件（104,204,304,404,504），其中所述至少一个部件接触表面（105）至少部分地覆盖所述至少一个承载板接触表面（ 102，202，302，402，502）; 以及c）加热所述焊膏（106,206,306,406,506）以在所述承载板和所述至少一个部件之间产生焊接连接。

公开(公告)号：EP2187435B1

公开(公告)日：2017-04-12

申请号：EP09773081.6

申请日：2009-02-16

Applicant: Omron Corporation

Inventor： ONO, Kazuyuki ,  TANAKA, Yoshio ,  NAKAJIMA, Kiyoshi ,  KURATANI, Naoto ,  MAEKAWA, Tomofumi

IPC: H01L23/04 ,  H01L23/10 ,  H01L23/055 ,  H01L23/552 ,  H05K3/34

CPC classification number: H05K3/341 ,  H01L23/055 ,  H01L23/10 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/16315 ,  H01L2924/1632 ,  H01L2924/3025 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/10371 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package for storing a semiconductor element mounted on an upper surface of a substrate (52) is configured by a substrate (52) and a conductive cap (54). A grounding electrode (57) is annularly formed on an upper surface outer circumferential section of the substrate (52). An upper surface of an inner circumferential section of the grounding electrode (57) is covered with a solder resist (67). On an outer circumference lower end surface of the conductive cap (54), a flange (70) substantially horizontally bent is formed. The conductive cap (54) is arranged on the upper surface of the substrate (52), and a lower surface of the flange (70) is permitted to abut to an upper surface of the solder resist (67). Furthermore, on a further outer circumferential side from the solder resist (67), a space formed between the lower surface of the flange (70) and the grounding electrode (57) is filled with a conductive bonding member (73), and the conductive cap (54) is bonded to the substrate (52).

公开(公告)号：EP3119169A1

公开(公告)日：2017-01-18

申请号：EP15181783.0

申请日：2015-08-20

Applicant: LG Innotek Co., Ltd.

Inventor： BAE, Yun Mi ,  KWON, Soon Gyu ,  KIM, Sang Hwa ,  LEE, Sang Young ,  LEE, Jin Hak ,  LEE, Han Su ,  JEONG, Dong Hun ,  JEONG, In Ho ,  CHOI, Dae Young ,  HWANG, Jung Ho

IPC: H05K3/10 ,  H05K3/24

CPC classification number: H05K1/11 ,  C25D3/38 ,  C25D3/48 ,  C25D5/022 ,  C25D5/48 ,  C25D7/123 ,  H05K1/09 ,  H05K3/108 ,  H05K3/181 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2203/1184

Abstract: A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.

Abstract translation: 印刷电路板包括绝缘层，绝缘层上的电路图案以及电路图案上的表面处理层。 表面处理层包括具有比电路图案的顶表面的宽度更宽的宽度的底表面。

公开(公告)号：EP2899751A1

公开(公告)日：2015-07-29

申请号：EP13839334.3

申请日：2013-05-17

Applicant: NGK Spark Plug Co., Ltd.

Inventor： HAYASHI, Takahiro ,  NAGAI, Makoto ,  MORI, Seiji ,  NISHIDA, Tomohiro ,  WAKAZONO, Makoto ,  ITO, Tatsuya

IPC: H01L23/12 ,  H01L21/60 ,  H05K3/34 ,  H05K3/46

CPC classification number: H05K1/111 ,  G03F7/038 ,  G03F7/20 ,  G03F7/2024 ,  G03F7/30 ,  H01L23/49822 ,  H01L2224/16237 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/09409 ,  H05K2201/09427 ,  H05K2201/09709 ,  H05K2201/09845 ,  H05K2201/099 ,  H05K2201/10674 ,  H05K2203/058 ,  H05K2203/0594 ,  H05K2203/1476

Abstract: To provide a wiring board excellent in connection reliability with a semiconductor chip. A first buildup layer 31 where resin insulating layers 21 and 22 and a conductor layer 24 are laminated is formed at a substrate main surface 11 side of an organic wiring board 10. The conductor layer 24 for an outermost layer in the first buildup layer 31 includes a plurality of connecting terminal portions 41 for flip-chip mounting a semiconductor chip. The plurality of connecting terminal portions 41 is exposed through an opening portion 43 of a solder resist layer 25. Each connecting terminal portion 41 includes a connection region 51 for a semiconductor chip and a wiring region 52 disposed to extend from the connection region 51 along the planar direction. The solder resist layer 25 includes, within the opening portion 43, a side-surface covering portion 55 that covers the side surface of the connecting terminal portion 41 and a projecting wall portion 56 that is integrally formed with the side-surface covering portion 55 and disposed to project so as to intersect with the connection region 51.

Abstract translation: 提供与半导体芯片的连接可靠性优异的布线板。 在有机配线基板10的基板主面11侧形成层叠有树脂绝缘层21,22和导体层24的第一堆积层31.第一堆积层31的最外层用导体层24包含 多个用于倒装安装半导体芯片的连接端子部分41。 多个连接端子部分41通过阻焊层25的开口部分43暴露。每个连接端子部分41包括用于半导体芯片的连接区域51和布置成从连接区域51沿着 平面方向。 阻焊层25在开口部分43内包括覆盖连接端子部分41的侧表面的侧表面覆盖部分55和与侧表面覆盖部分55一体形成的突出壁部分56以及 设置成突出以便与连接区域51相交。

公开(公告)号：EP2852263A1

公开(公告)日：2015-03-25

申请号：EP13791708.4

申请日：2013-04-11

Applicant: Fuji Electric FA Components & Systems Co. Ltd.

Inventor： OKAMOTO, Kokichi ,  TAGUCHI, Takahiro

IPC: H05K3/34

CPC classification number: H05K13/0465 ,  B23K1/20 ,  H01L2224/32225 ,  H01L2924/19105 ,  H05K3/303 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/2036 ,  Y02P70/613

Abstract: To provide a method of mounting electric parts on a surface mounting substrate whereby it is possible to accurately set the stand-off height of a chip part. The method includes a step of forming a thick film resist layer by applying a resist with a thick film coating device to a mounting surface of a surface mounting substrate on which is formed a wiring pattern including a pair of lands on which to mount an electronic part, a step of precuring the formed thick film resist layer, a step of exposing exposure regions using a mask with inner side regions of the thick film resist layer, which are on the lands and to be below the electronic part, as the exposure regions and with the other regions as non-exposure regions, a step of etching away the thick film resist layer in the non-exposure regions and thus forming thick film resist layers in the inner side regions which are on the pair of lands and to be below the electronic part, a step of post curing the thick film resist layers, a step of printing solder pastes in regions on the lands excluding the inner side regions, and a step of placing the electronic part on the solder pastes and carrying out reflow soldering thereon.

Abstract translation: 提供一种将电气部件安装在表面安装基板上的方法，由此可以精确地设定芯片部件的间隔高度。 该方法包括通过将具有厚膜涂覆装置的抗蚀剂涂覆到表面安装基板的安装表面上形成厚膜抗蚀剂层的步骤，在其上形成包括一对焊盘的布线图案，其上安装电子部件 对形成的厚膜保护层进行预处理的步骤，使用掩模的曝光区域曝露在台面上并且位于电子部件下方的曝光区域作为曝光区域的工序;以及 其他区域作为非曝光区域，在非曝光区域中蚀刻掉厚膜抗蚀剂层的步骤，从而在位于该一对焊盘上的内侧区域中形成厚膜抗蚀剂层并在 电子部件，后固化厚膜抗蚀剂层的步骤，在除了内侧区域之外的区域上的区域中印刷焊膏的步骤，以及将电子部件放置在焊膏上并进行 在其上进行回流焊接。