公开(公告)号：JP4329884B2

公开(公告)日：2009-09-09

申请号：JP2009512085

申请日：2008-09-17

Applicant: 株式会社村田製作所

Inventor： 雅人 野村

IPC: H01L25/00 ,  H05K3/46

CPC classification number: H05K1/186 ,  H01L23/3677 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H05K1/0206 ,  H05K1/0306 ,  H05K3/4605 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09845 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  Y10T29/49206 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

公开(公告)号：JP2009194381A

公开(公告)日：2009-08-27

申请号：JP2009021489

申请日：2009-02-02

Applicant: Ibiden Co Ltd ,  イビデン株式会社

Inventor： TANAKA HIRONORI ,  YOSHIKAWA KAZUHIRO ,  FUJII NAOAKI ,  YAMASHITA TAKASHIGE

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/185 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/188 ,  H05K3/382 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: PROBLEM TO BE SOLVED: To provide a production process of a printed wiring board which incorporates an electronic component and enhances connection reliability. SOLUTION: An IC chip 30 is mounted with reference to a positioning mark 26 formed on a single-sided copper clad laminate 20, a through-hole 36 is bored to reach the terminals 30A and 30B of the IC chip 30, and the through-hole 36 is filled with metals 38 and 40, thus providing a via hole 42 for connecting the terminals of a chip capacitor 30. Since a position gap does not arise between the terminal 30A, 30B of the chip capacitor 30 and the via hole 42, connection reliability of the via hole 42 for connecting the terminals of the chip capacitor can be enhanced. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种结合电子部件的印刷电路板的制造工艺，提高连接可靠性。 解决方案：参考形成在单面覆铜层压板20上的定位标记26安装IC芯片30，通孔36被钻孔以到达IC芯片30的端子30A和30B，并且 通孔36填充有金属38和40，从而提供用于连接片状电容器30的端子的通孔42.由于在片状电容器30的端子30A，30B和通孔之间没有出现位置间隙 可以提高用于连接片式电容器的端子的通孔42的连接可靠性。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009152300A

公开(公告)日：2009-07-09

申请号：JP2007327499

申请日：2007-12-19

Applicant: Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

Inventor： KURAMOCHI TOSHIYUKI

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K1/0271 ,  H05K3/4602 ,  H05K3/4694 ,  H05K2201/0187 ,  H05K2201/068 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09972 ,  Y10T29/49124

Abstract: PROBLEM TO BE SOLVED: To provide a wiring substrate capable of preventing deformation such as a warpage or the like, or substantially reducing the amount of deformation; to provide its manufacturing method; and to prevent conveyance failure and mounting failure caused by deformation of the wiring substrate in an electronic mounting process. SOLUTION: In the wiring board, one or more layers having a coefficient of thermal expansion different from that of a core layer are laminated on at least one surface side of the core layer, and a plurality of mounting regions to which a plurality of electronic components are mounted are formed on the surface layers of the laminated layers with prescribed spaces left between them. The core layer is divided for each mounting region or correspondingly to a group of the mounting regions covering a plurality of the mounting regions, and an insulating material forming the laminated layers is filled in a gap between the mutually adjoining core layers. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够防止诸如翘曲等的变形或大大减少变形量的布线基板; 提供其制造方法; 并且防止在电子安装过程中由布线基板的变形引起的输送故障和安装故障。 解决方案：在布线板中，在芯层的至少一个表面侧层叠具有与芯层不同的热膨胀系数的一个或多个层，以及多个安装区域，多个安装区域 电子部件的安装形成在层叠层的表面层上，其间留有规定的间隔。 芯层为每个安装区域或对应于覆盖多个安装区域的一组安装区域分开，并且形成层叠层的绝缘材料填充在相互相邻的芯层之间的间隙中。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009060086A

公开(公告)日：2009-03-19

申请号：JP2008185024

申请日：2008-07-16

Applicant: E I Du Pont De Nemours & Co ,  イー・アイ・デュポン・ドウ・ヌムール・アンド・カンパニーE.I.Du Pont De Nemours And Company

Inventor： SUMMERS JOHN D ,  DUEBER THOMAS EUGENE

IPC: H01L23/29 ,  H01L23/12 ,  H01L23/31

CPC classification number: H05K1/162 ,  C08G69/00 ,  C08G73/22 ,  H01L51/5253 ,  H05K3/1291 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126

Abstract: PROBLEM TO BE SOLVED: To provide compositions, and the use of such compositions for protective coatings, particularly of electronic devices. SOLUTION: The invention concerns fired-on-foil ceramic capacitors coated with a composite encapsulant and embedded in a printed wiring board. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供组合物以及这些组合物用于保护涂层，特别是电子设备的用途。 解决方案：本发明涉及涂覆有复合密封剂并嵌入印刷线路板的烧制箔陶瓷电容器。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JPWO2007013595A1

公开(公告)日：2009-02-12

申请号：JP2007526911

申请日：2006-07-28

Applicant: 株式会社フジクラ ,  共栄電資株式会社

Inventor： 敦司 百田 ,  敦司 百田 ,  照沼　一郎 ,  一郎 照沼 ,  長谷川　健 ,  健 長谷川 ,  竹村　安男 ,  安男 竹村 ,  祥史 畠山 ,  祥史 畠山 ,  原田　洋 ,  洋 原田 ,  加藤　亮 ,  亮 加藤

IPC: H05K3/46

CPC classification number: H05K3/4691 ,  H05K1/036 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/10303 ,  H05K2203/308 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: 電装部品の実装が容易であり(製造性・組立性の高い基板回路の実現)、且つ省スペース化を図ることができ、さらに製造が容易な、屈曲式のリジットプリント配線板を提供するものである。すなわち、間隙部分1Aを挟んで配設される硬質のコア材1の表面に、前記間隙部分1Aの上面とともに耐熱性樹脂層31を積層し、前記コア材1の裏面に間隙部分1Aを除き耐熱性樹脂層32を積層するとともに、前記耐熱性樹脂層31,32を介して導体層4を積層固着し、当該導体層4をエッチング処理して回路形成した屈曲式リジットプリント配線板を提供する。

公开(公告)号：JP2008277734A

公开(公告)日：2008-11-13

申请号：JP2007317864

申请日：2007-12-10

Applicant: Ind Technol Res Inst ,  インダストリアル・テクノロジー・リサーチ・インスティテュートIndustrial Technology Research Institute

Inventor： WU SHIH-HSIEN ,  LAI SHINN-JUH ,  LEE MIN-LIN ,  LIU SHUR-FEN

IPC: H01G4/20 ,  H01G4/12 ,  H01G4/33

CPC classification number: H01G4/06 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/14 ,  H01G4/20 ,  H01G4/206 ,  H05K1/162 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09672 ,  H05K2201/2036 ,  Y10T29/417

Abstract: PROBLEM TO BE SOLVED: To provide a capacitor device which has capacitance. SOLUTION: The capacitor device is provided with: a pair of conductive layers 214 and 224 which face each other; a first dielectric layer 226 which is formed on a surface of the first conductive layer 224 and has a first dielectric constant; and a second dielectric layer 230 which has a second dielectric constant and is sandwiched between the first conductive layers 214 and 224 through the first dielectric layer 226. The capacitance of the capacitor device is determinted by the dielectric constant and the thickness of the first dielectric layer 226, and the second dielectric constant and the thickness of the second dielectric layer 230. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有电容的电容器装置。 解决方案：电容器装置设置有：彼此面对的一对导电层214和224; 第一电介质层226，其形成在第一导电层224的表面上并具有第一介电常数; 以及具有第二介电常数并通过第一介电层226夹在第一导电层214和224之间的第二电介质层230.电容器器件的电容由第一介电层的介电常数和厚度决定 226，以及第二介电常数和第二介电层230的厚度。版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008192640A

公开(公告)日：2008-08-21

申请号：JP2007022308

申请日：2007-01-31

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： OKUZAWA NOBUYUKI

IPC: H01G4/33 ,  H01G4/12

CPC classification number: H01G4/33 ,  H01G4/224 ,  H01L27/016 ,  H01L28/40 ,  H03H2001/0014 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/0023 ,  H05K3/388 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2203/0733 ,  Y10T29/435

Abstract: PROBLEM TO BE SOLVED: To provide a thin-film capacitor in which V BD can be raised while suppressing variation in capacity and thereby the device characteristics and the reliability of product can be enhanced. SOLUTION: Each electronic component 1-4 has a capacitor 11 formed on a smooth substrate 51 having a planarization layer 52 formed on the surface as a base material. The capacitor 11 has such a structure as a lower conductor 21 consisting of an underlying conductor 21a and a conductor 21b, a dielectric film 31 composed of alumina, a resin layer J1 principally composed of novolak based resin, a resin layer J2 principally composed of polyimide based resin, and an upper conductor 25 consisting of an underlying conductor 25a and a conductor 25b are formed on the planarization layer 52 of the substrate 51. The resin layer J1 has an opening K1 above the lower conductor 21 and the resin layer J2 has an opening K2 larger than the opening K1. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种可以在抑制容量变化的同时提高V SB SB的薄膜电容器，从而可以提高器件特性和产品的可靠性。 解决方案：每个电子部件1-4具有形成在平坦化基板51上的电容器11，平坦化层52形成在作为基材的表面上的平坦化层52。 电容器11具有如下结构，即由下导体21a和导体21b构成的下导体21，由氧化铝构成的电介质膜31，主要由酚醛清漆型树脂构成的树脂层J1，主要由聚酰亚胺构成的树脂层J2 并且在基板51的平坦化层52上形成由下面的导体25a和导体25b组成的上部导体25.树脂层J1在下部导体21的上方具有开口K1，树脂层J2具有 开口K2大于开口K1。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP4103653B2

公开(公告)日：2008-06-18

申请号：JP2003087207

申请日：2003-03-27

Applicant: 株式会社デンソー

Inventor： 中川　　充 ,  晃敬 丸山

IPC: B42D15/10 ,  G06K19/077 ,  G06K19/07 ,  H05K1/02 ,  H05K1/18 ,  H05K3/00 ,  H05K3/28

CPC classification number: H05K3/284 ,  H05K1/0271 ,  H05K1/189 ,  H05K3/0058 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/2009

Abstract: Of an IC card, an IC is mounted on a surface of a circuit board (FPC) including a hard plate member that is attached on the other surface of the circuit board. Both surfaces of the circuit board having the IC and plate member are covered by a hard material member of electric insulating. Therefore, stress load applied to the IC can be restricted. Further, the circuit board along with the hard material member is divided into multiple portions that are connected using a flexible electric wiring. This can provide sufficient flexibility to the IC card, resulting in enhancement of a preventive effect in breakage or damage of the IC card.

公开(公告)号：JP4069587B2

公开(公告)日：2008-04-02

申请号：JP2000585927

申请日：1999-12-02

Applicant: セイコーエプソン株式会社

Inventor： 俊宏 沢本

IPC: H01L21/60 ,  H01L21/603 ,  H01L23/498 ,  H05K3/32

CPC classification number: H05K3/323 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29293 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/15787 ,  H05K2201/0187 ,  H05K2201/09909 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2924/00

Abstract: An anisotropic conductive film includes hard portions at the two edges and a soft portion constituting the remainder. Due to such a construction, when a semiconductor chip is bonded to a substrate by thermocompression, the hard portions inhibit the soft portion from flowing toward the periphery of the semiconductor chip. Thereby, it is possible to prevent the anisotropic conductive film from adhering to a hot pressing tool.

公开(公告)号：JP4021472B1

公开(公告)日：2007-12-12

申请号：JP2007513540

申请日：2006-10-24

Applicant: イビデン株式会社

Inventor： 雅一 青山 ,  通昌 高橋

IPC: H05K3/46

CPC classification number: H05K3/4644 ,  H05K3/0035 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4691 ,  H05K2201/0187 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627

Abstract: 導体パターン１３２、１３３を備える可撓性基板１３と剛性を有する非可撓性基材１１１とを、水平方向に並べて配置する。 可撓性基板１３と非可撓性基材１１１とを、可撓性基板の少なくとも一部を露出するように絶縁層１１１、１１３で被覆する。 可撓性基板１３の導体パターン１３２、１３３に至るヴィア１１６、１４１を絶縁層１１１、１１６に形成し、ヴィア１１６、１４１を介してメッキで、導体パターン１３２、１３３に至る配線１１７、１４２を形成する。 絶縁層１１１、１１３の上に絶縁層１１４、１１５、１４４、１４５を積層し、回路１２３、１５０を形成し、配線を接続する。
【選択図】図３