公开(公告)号：US07897878B2

公开(公告)日：2011-03-01

申请号：US11627430

申请日：2007-01-26

Applicant: Paul Coteus ,  Gareth Geoffrey Hougham ,  Brian R. Sundlof

Inventor： Paul Coteus ,  Gareth Geoffrey Hougham ,  Brian R. Sundlof

IPC: H01R12/04 ,  H05K1/11 ,  H05K3/36

CPC classification number: H05K3/3436 ,  H01L23/13 ,  H01L23/49805 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K3/28 ,  H05K3/325 ,  H05K3/4007 ,  H05K3/4015 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2201/1059 ,  H05K2201/10719 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A circuit package is provided. The circuit package includes a plurality of electrically conductive pads located on a bottom surface of the circuit package, wherein at least one pad of the plurality of bottom surface pads has a recession for receiving an electrically conductive protrusion located on a substrate to which the circuit package is to be mounted.

Abstract translation: 提供电路封装。 电路封装包括位于电路封装的底表面上的多个导电焊盘，其中多个底表面焊盘中的至少一个焊盘具有用于接收位于基板上的导电突起的凹陷，电路封装 将被安装。

公开(公告)号：US20100155456A1

公开(公告)日：2010-06-24

申请号：US12536122

申请日：2009-08-05

Applicant: GARETH G. HOUGHAM ,  KAMALESH K. SRIVASTAVA ,  SUNG K. KANG ,  DA-YUAN SHIH ,  BRIAN R. SUNDLOF ,  S. JAY CHEY ,  DONALD W. HENDERSON ,  DAVID R. DI MILIA ,  RICHARD P. FERLITA ,  ROY A. CARRUTHERS

Inventor： GARETH G. HOUGHAM ,  KAMALESH K. SRIVASTAVA ,  SUNG K. KANG ,  DA-YUAN SHIH ,  BRIAN R. SUNDLOF ,  S. JAY CHEY ,  DONALD W. HENDERSON ,  DAVID R. DI MILIA ,  RICHARD P. FERLITA ,  ROY A. CARRUTHERS

IPC: B23K31/02

CPC classification number: B23K1/19 ,  B23K35/262 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0215

Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state. Further, the addition of a trace amount of nucleation sites within the composition facilitates control over the number, size, and orientations of primary intermetallic compounds in tin rich crystallite grains. Moreover, trace amounts of one or more solid and/or insoluble nucleating modifiers within a given volume of solder reduces the size of average crystallites within the composition.

Abstract translation: 简而言之，公开了一种新颖的材料方法，其中将一种或多种成核改性剂以微量添加到无铅富锡焊料合金中以产生具有降低或抑制的过冷温度特性的焊料组合物。 该改性剂是有助于减少与体心四方锡锡基无铅焊料相关的极端各向异性的物质。 将成核改性剂添加到焊料合金中不会实质上影响焊料组合物的熔点。 因此，具有成核组合物的焊料球冻结，而阵列内的其它焊球保持在熔体中。 这有效地使一个基板通过一个或多个预定的焊球被固定到另一个基板，以固定封装，而剩余的焊点处于液态。 此外，在组合物中添加微量的成核位点有助于控制富锡微晶颗粒中初级金属间化合物的数量，尺寸和取向。 此外，在给定体积的焊料中痕量的一种或多种固态和/或不溶性成核改性剂减少了组合物内平均微晶的尺寸。

公开(公告)号：US07703661B2

公开(公告)日：2010-04-27

申请号：US11752382

申请日：2007-05-23

Applicant: Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

Inventor： Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

IPC: B23K35/24

CPC classification number: B23K1/19 ,  B23K35/262 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0215

Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduced or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state.

Abstract translation: 简而言之，公开了一种新颖的材料方法，其中将一种或多种成核改性剂以痕量添加到无铅富锡焊料合金中以产生具有降低或抑制的过冷却温度特性的焊料组合物。 该改性剂是有助于减少与体心四方锡锡基无铅焊料相关的极端各向异性的物质。 将成核改性剂添加到焊料合金中不会实质上影响焊料组合物的熔点。 因此，具有成核组合物的焊料球冻结，而阵列内的其它焊球保持在熔体中。 这有效地使一个基板通过一个或多个预定的焊球被固定到另一个基板，以固定封装，而剩余的焊点处于液态。

公开(公告)号：US07683493B2

公开(公告)日：2010-03-23

申请号：US12111510

申请日：2008-04-29

Applicant: Charles L. Arvin ,  Carla A. Bailey ,  Harry D. Cox ,  Hua Gan ,  Hsichang Liu ,  Arthur G. Merryman ,  Vall F. McClean ,  Srinivasa S. N. Reddy ,  Brian R. Sundlof

Inventor： Charles L. Arvin ,  Carla A. Bailey ,  Harry D. Cox ,  Hua Gan ,  Hsichang Liu ,  Arthur G. Merryman ,  Vall F. McClean ,  Srinivasa S. N. Reddy ,  Brian R. Sundlof

IPC: H01L23/52

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/03462 ,  H01L2224/03472 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05017 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05564 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: One embodiment of the present invention is directed to an under bump metallurgy material. The under bump metallurgy material of this embodiment includes an adhesion layer and a conduction layer formed on top of the adhesion layer. The under bump metallurgy material of this embodiment also includes a barrier layer plated on top of the conduction layer and a sacrificial layer plated on top of the barrier layer. The conduction layer of this embodiment includes a trench formed therein, the trench contacting a portion of the barrier layer and blocking a path of intermetallic formation between the conduction layer and the sacrificial layer.

Abstract translation: 本发明的一个实施例涉及一种凸块下金属材料。 本实施方式的凸块状冶金材料包括粘合层和形成在粘合层顶部的导电层。 该实施例的凸块下冶金材料还包括电镀在导电层顶部上的阻挡层和镀在阻挡层顶部上的牺牲层。 该实施例的导电层包括在其中形成的沟槽，沟槽接触势垒层的一部分并且阻挡导电层和牺牲层之间的金属间形成路径。

公开(公告)号：US20080290142A1

公开(公告)日：2008-11-27

申请号：US11752382

申请日：2007-05-23

Applicant: Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

Inventor： Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

IPC: B23K35/24 ,  B23K101/36 ,  B23K31/02

CPC classification number: B23K1/19 ,  B23K35/262 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0215

Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state. Further, the addition of a trace amount of nucleation sites within the composition facilitates control over the number, size, and orientations of primary intermetallic compounds in tin rich crystallite grains. Moreover, trace amounts of one or more solid and/or insoluble nucleating modifiers within a given volume of solder reduces the size of average crystallites within the composition.

Abstract translation: 简而言之，公开了一种新颖的材料方法，其中将一种或多种成核改性剂以微量添加到无铅富锡焊料合金中以产生具有降低或抑制的过冷温度特性的焊料组合物。 该改性剂是有助于减少与体心四方锡锡基无铅焊料相关的极端各向异性的物质。 将成核改性剂添加到焊料合金中不会实质上影响焊料组合物的熔点。 因此，具有成核组合物的焊料球冻结，而阵列内的其它焊球保持在熔体中。 这有效地使一个基板通过一个或多个预定的焊球被固定到另一个基板，以固定封装，而剩余的焊点处于液态。 此外，在组合物中添加微量的成核位点有助于控制富锡微晶颗粒中初级金属间化合物的数量，尺寸和取向。 此外，在给定体积的焊料中痕量的一种或多种固态和/或不溶性成核改性剂减少了组合物内平均微晶的尺寸。

公开(公告)号：US07351360B2

公开(公告)日：2008-04-01

申请号：US10986665

申请日：2004-11-12

Applicant: Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

Inventor： Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

IPC: H01B1/04

CPC classification number: H01L23/3733 ,  B82Y30/00 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/40 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  Y10S977/788 ,  Y10T156/10 ,  Y10T428/24994 ,  H01L2224/0401

Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.

Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。

公开(公告)号：US07294909B2

公开(公告)日：2007-11-13

申请号：US11099161

申请日：2005-04-05

Applicant: Jon A. Casey ,  James G. Balz ,  Michael Berger ,  Jerome Cohen ,  Charles Hendricks ,  Richard Indyk ,  Mark LaPlante ,  David C. Long ,  Lori A. Maiorino ,  Arthur G. Merryman ,  Glenn A. Pomerantz ,  Robert A. Rita ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Brian R. Sundlof ,  Richard P. Surprenant ,  Donald R. Wall ,  Thomas A. Wassick ,  Kathleen M. Wiley

Inventor： Jon A. Casey ,  James G. Balz ,  Michael Berger ,  Jerome Cohen ,  Charles Hendricks ,  Richard Indyk ,  Mark LaPlante ,  David C. Long ,  Lori A. Maiorino ,  Arthur G. Merryman ,  Glenn A. Pomerantz ,  Robert A. Rita ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Brian R. Sundlof ,  Richard P. Surprenant ,  Donald R. Wall ,  Thomas A. Wassick ,  Kathleen M. Wiley

IPC: H01L27/148 ,  H01L29/768

CPC classification number: H05K3/225 ,  H01L21/4846 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K3/0029 ,  H05K3/4629 ,  H05K2203/173 ,  Y10T29/49124 ,  Y10T29/49135 ,  H01L2924/00

Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Abstract translation: 一种多层陶瓷修复工艺，提供了一个新的电气修复路径，以连接顶面通孔。 修复路径是建立在有缺陷的网和包含在多层陶瓷基板内的冗余修复网之间。 有缺陷的网和修复网各自终止在基板的表面通孔处。 使用激光器在基板上和基板上形成点火电路。 之后是有缺陷的网络与电气修复结构的电气隔离和电气修复线路的钝化。

公开(公告)号：US09111816B2

公开(公告)日：2015-08-18

申请号：US13431609

申请日：2012-03-27

Applicant: Virendra R. Jadhav ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof

Inventor： Virendra R. Jadhav ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16235 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/384 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A multi-layer pillar is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Abstract translation: 提供多层支柱。 多层柱用作芯片和基板之间的互连。 支柱具有至少一个低强度，高延展性变形区域，其被配置为吸收在芯片组装和热偏移期间施加的力。

公开(公告)号：US08604623B2

公开(公告)日：2013-12-10

申请号：US13553887

申请日：2012-07-20

Applicant: Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

Inventor： Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

IPC: H01L23/04

CPC classification number: H01L23/3733 ,  B82Y30/00 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/40 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  Y10S977/788 ,  Y10T156/10 ,  Y10T428/24994 ,  H01L2224/0401

Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.

Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。

公开(公告)号：US08293587B2

公开(公告)日：2012-10-23

申请号：US11870583

申请日：2007-10-11

Applicant: Virendra R Jadhav ,  Krystyna W Semkow ,  Kamalesh K Srivastava ,  Brian R Sundlof

Inventor： Virendra R Jadhav ,  Krystyna W Semkow ,  Kamalesh K Srivastava ,  Brian R Sundlof

IPC: H01L21/00

CPC classification number: H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16235 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/384 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Abstract translation: 提供了一种多层柱及其制造方法。 多层柱用作芯片和基板之间的互连。 支柱具有至少一个低强度，高延展性变形区域，其被配置为吸收在芯片组装和热偏移期间施加的力。