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公开(公告)号:US09748196B2
公开(公告)日:2017-08-29
申请号:US14486755
申请日:2014-09-15
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor: Jen-Kuang Fang , Kuo-Hua Chen
IPC: H01L23/48 , H01L23/00 , H01L23/522
CPC classification number: H01L24/33 , H01L23/5226 , H01L24/05 , H01L24/09 , H01L24/17 , H01L2224/0401 , H01L2224/04026 , H01L2224/0557 , H01L2224/05571 , H01L2224/05572 , H01L2224/06164 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2924/381
Abstract: The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.
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公开(公告)号:US09196595B2
公开(公告)日:2015-11-24
申请号:US14192029
申请日:2014-02-27
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Kuo-Hua Chen , Tzu-Hua Lin , Kuan-Neng Chen , Yan-Pin Huang
IPC: H01L23/00 , H01L21/56 , H01L25/065 , H01L25/00 , H01L23/498 , H01L23/31
CPC classification number: H01L24/11 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/13082 , H01L2224/13111 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13149 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/13166 , H01L2224/13169 , H01L2224/13176 , H01L2224/13178 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16501 , H01L2224/73204 , H01L2224/75251 , H01L2224/75252 , H01L2224/81193 , H01L2224/81203 , H01L2224/8183 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/15788 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2924/00
Abstract: The disclosure relates to a semiconductor bonding structure and process and a semiconductor chip. The semiconductor bonding structure includes a first pillar, a first interface, an intermediate area, a second interface and a second pillar in sequence. The first pillar, the second pillar and the intermediate area include a first metal. The first interface and the second interface include the first metal and an oxide of a second metal. The content percentage of the first metal in the first interface and the second interface is less than that of the first metal in the intermediate area.
Abstract translation: 本公开涉及半导体接合结构和工艺以及半导体芯片。 半导体接合结构依次包括第一柱,第一界面,中间区域,第二界面和第二柱。 第一支柱,第二支柱和中间区域包括第一金属。 第一界面和第二界面包括第一金属和第二金属的氧化物。 第一界面和第二界面中的第一金属的含量百分比小于中间区域中的第一金属的含量百分比。
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公开(公告)号:US09173583B2
公开(公告)日:2015-11-03
申请号:US13840817
申请日:2013-03-15
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Kuo-Hua Chen , Chih-Wei Chang , Jin-Chern Chiou
IPC: A61B5/0478 , A61B5/00 , A61B5/04 , A61B5/0492 , H01L23/48 , A61B5/0496 , A61N1/05
CPC classification number: A61B5/0478 , A61B5/04001 , A61B5/0492 , A61B5/0496 , A61B5/6868 , A61B2562/028 , A61B2562/043 , A61N1/0529 , H01L21/6835 , H01L21/6836 , H01L23/481 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/92 , H01L24/94 , H01L2221/68327 , H01L2221/6834 , H01L2224/0231 , H01L2224/02331 , H01L2224/05569 , H01L2224/92 , H01L2224/94 , H01L21/76898 , H01L2224/03 , H01L2221/68304 , H01L21/304 , H01L21/56 , H01L2221/68381 , H01L21/78 , H01L2924/00014
Abstract: The present invention provides a neural sensing device and method for making the same. The neural sensing device includes a base, an integrated circuit portion, a plurality of microprobes and at least one conductive via. The base has an active surface and a backside surface. The integrated circuit portion is disposed on the active surface of the base. The microprobes protrude from the backside surface of the base. The through silicon via is disposed in the base and electrically connects the integrated circuit portion and the microprobes. Each of the microprobes includes an isolation layer partially covering a conductive layer.
Abstract translation: 本发明提供了一种神经感测装置及其制造方法。 神经感测装置包括基座,集成电路部分,多个微探针和至少一个导电通孔。 底座具有活动表面和背面。 集成电路部分设置在基座的有源表面上。 微型笔从底座的背面突出。 贯通硅通孔设置在基座中并电连接集成电路部分和微器件。 每个微探针包括部分地覆盖导电层的隔离层。
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公开(公告)号:US11728252B2
公开(公告)日:2023-08-15
申请号:US16846085
申请日:2020-04-10
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Hui Hua Lee , Chun Hao Chiu , Hui-Ying Hsieh , Kuo-Hua Chen , Chi-Tsung Chiu
IPC: H01L23/495 , H01L21/48 , H01L23/498 , H01L23/538 , H01L23/00 , H01L25/065 , H01L25/16
CPC classification number: H01L23/49575 , H01L21/486 , H01L21/4857 , H01L23/49513 , H01L23/49517 , H01L23/49811 , H01L23/49866 , H01L23/5386 , H01L23/5389 , H01L24/00 , H01L25/0652 , H01L25/16 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/24137 , H01L2224/24145 , H01L2224/24195 , H01L2224/24247 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2225/06524 , H01L2225/06548 , H01L2225/06572 , H01L2225/06575 , H01L2225/06589 , H01L2924/15153 , H01L2924/3511 , H01L2924/3511 , H01L2924/00
Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.
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公开(公告)号:US11133245B2
公开(公告)日:2021-09-28
申请号:US16664631
申请日:2019-10-25
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Chi-Tsung Chiu , Hui-Ying Hsieh , Kuo-Hua Chen , Cheng Yuan Chen
IPC: H01L23/48 , H01L23/498 , H01L21/768 , H01L23/495
Abstract: A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.
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公开(公告)号:US09578737B2
公开(公告)日:2017-02-21
申请号:US14169640
申请日:2014-01-31
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Kuo-Hua Chen , Ming-Chiang Lee , Tsung-Hsun Lee , Chen-Chuan Fan
CPC classification number: H05K1/0298 , H01L23/3128 , H01L23/49838 , H01L2224/16225 , H01L2224/73204 , H01L2924/15311 , H05K1/0271 , H05K1/09 , H05K1/116 , H05K2201/09781
Abstract: A substrate structure is provided. The substrate structure includes a number of traces, a substrate core, a number of first metal tiles, a number of second metal tiles, a number of first electrically-functioning circuits, and a number of second electrically-functioning circuits. The substrate core has a first surface and a second surface opposite to the first surface. The traces, the first metal tiles, and the first electrically-functioning circuits are disposed on the first surface and add up to a first metal structure proportion, and the second metal tiles and the second electrically-functioning circuits are disposed on the second surface and add up to a second metal structure proportion. The difference between the first metal structure proportion and the second metal structure proportion is within 15%.
Abstract translation: 提供了基板结构。 衬底结构包括多个迹线,衬底芯,多个第一金属片,多个第二金属片,多个第一电功能电路和多个第二电功能电路。 衬底芯具有与第一表面相对的第一表面和第二表面。 迹线,第一金属瓦片和第一电功能电路设置在第一表面上并加到第一金属结构比例上,第二金属瓦片和第二电功能电路设置在第二表面上, 加起来第二个金属结构比例。 第一金属结构比例与第二金属结构比例之差在15%以内。
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7.
公开(公告)号:US09564393B1
公开(公告)日:2017-02-07
申请号:US14857931
申请日:2015-09-18
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Chih-Yi Huang , Kuo-Hua Chen , Chi-Tsung Chiu
IPC: H01L23/00 , H01L23/498 , H01L21/52 , H01L21/768
CPC classification number: H01L23/49844 , H01L21/486 , H01L21/52 , H01L21/76802 , H01L21/76877 , H01L23/49811 , H01L23/49827 , H01L23/5389 , H01L23/552 , H01L24/24 , H01L24/82 , H01L2224/04105 , H01L2224/06181 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/8203 , H01L2224/92244 , H01L2924/3025 , H01L2924/3511
Abstract: A semiconductor device package includes a substrate and a semiconductor device disposed on a surface of the substrate. The semiconductor device includes a first contact pad and a second contact pad disposed on an upper surface of the semiconductor device. The semiconductor device package further includes a conductive bar disposed on the first contact pad, and a conductive pillar disposed on the second contact pad. A method of making a semiconductor device package includes (a) providing a substrate; (b) mounting a semiconductor device on the substrate, wherein the semiconductor device comprises a first contact pad and a second contact pad on an upper surface of the semiconductor device; (c) forming a dielectric layer on the substrate to cover the semiconductor device; (d) exposing the second contact pad by forming a hole in the dielectric layer; and (e) applying a conductive material over the dielectric layer and filling the hole.
Abstract translation: 半导体器件封装包括衬底和设置在衬底的表面上的半导体器件。 半导体器件包括设置在半导体器件的上表面上的第一接触焊盘和第二接触焊盘。 半导体器件封装还包括设置在第一接触焊盘上的导电棒和设置在第二接触焊盘上的导电柱。 制造半导体器件封装的方法包括(a)提供衬底; (b)将半导体器件安装在所述衬底上,其中所述半导体器件包括在所述半导体器件的上表面上的第一接触焊盘和第二接触焊盘; (c)在所述基板上形成电介质层以覆盖所述半导体器件; (d)通过在电介质层中形成一个孔来暴露第二接触垫; 和(e)将导电材料涂覆在电介质层上并填充该孔。
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公开(公告)号:US20140275929A1
公开(公告)日:2014-09-18
申请号:US13840817
申请日:2013-03-15
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor: Kuo-Hua Chen , Chih-Wei Chang , Jin-Chern Chiou
IPC: A61B5/0478 , H01L21/768
CPC classification number: A61B5/0478 , A61B5/04001 , A61B5/0492 , A61B5/0496 , A61B5/6868 , A61B2562/028 , A61B2562/043 , A61N1/0529 , H01L21/6835 , H01L21/6836 , H01L23/481 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/92 , H01L24/94 , H01L2221/68327 , H01L2221/6834 , H01L2224/0231 , H01L2224/02331 , H01L2224/05569 , H01L2224/92 , H01L2224/94 , H01L21/76898 , H01L2224/03 , H01L2221/68304 , H01L21/304 , H01L21/56 , H01L2221/68381 , H01L21/78 , H01L2924/00014
Abstract: The present invention provides a neural sensing device and method for making the same. The neural sensing device includes a base, an integrated circuit portion, a plurality of microprobes and at least one conductive via. The base has an active surface and a backside surface. The integrated circuit portion is disposed on the active surface of the base. The microprobes protrude from the backside surface of the base. The through silicon via is disposed in the base and electrically connects the integrated circuit portion and the microprobes. Each of the microprobes includes an isolation layer partially covering a conductive layer.
Abstract translation: 本发明提供了一种神经感测装置及其制造方法。 神经感测装置包括基座,集成电路部分,多个微探针和至少一个导电通孔。 底座具有活动表面和背面。 集成电路部分设置在基座的有源表面上。 微型笔从底座的背面突出。 贯通硅通孔设置在基座中并电连接集成电路部分和微器件。 每个微探针包括部分地覆盖导电层的隔离层。
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公开(公告)号:US20140275911A1
公开(公告)日:2014-09-18
申请号:US13802355
申请日:2013-03-13
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor: Kuo-Hua Chen
IPC: A61B5/04 , H01L21/768
CPC classification number: A61B5/04001 , A61B5/0478 , A61B5/685 , A61B5/6868 , A61B2562/046 , A61B2562/12 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/92 , H01L24/94 , H01L2221/68327 , H01L2221/6834 , H01L2224/0231 , H01L2224/0235 , H01L2224/02372 , H01L2224/05569 , H01L2224/92 , H01L2224/94 , H01L2924/00012 , H01L2224/03 , H01L2221/68304 , H01L21/304 , H01L21/56 , H01L2221/68381 , H01L21/78 , H01L2924/00014
Abstract: The present invention provides a neural sensing device and method for making the same. The neural sensing device includes a base, an integrated circuit portion and a plurality of microprobes. The base has an active surface and a backside surface. The integrated circuit portion is disposed on the active surface of the base. The microprobes protrude from the backside surface of the base. The conductive vias are disposed in the microprobes and electrically connected to the integrated circuit portion.
Abstract translation: 本发明提供了一种神经感测装置及其制造方法。 该神经感测装置包括基座,集成电路部分和多个微探针。 底座具有活动表面和背面。 集成电路部分设置在基座的有源表面上。 微型笔从底座的背面突出。 导电通孔设置在微探针中并电连接到集成电路部分。
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公开(公告)号:US10707157B2
公开(公告)日:2020-07-07
申请号:US15621970
申请日:2017-06-13
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Hui Hua Lee , Chun Hao Chiu , Hui-Ying Hsieh , Kuo-Hua Chen , Chi-Tsung Chiu
IPC: H01L23/495 , H01L23/00 , H01L23/538 , H01L23/498 , H01L21/48 , H01L25/16 , H01L25/065
Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.
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